From 30daa7529331057ecb470efb500152e9c4aa1ae5 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Thu, 13 Oct 2005 14:30:20 +0000 Subject: [PATCH] enable 3rd texture unit on radeon (default still 2 enabled units). Disable some multitexcoord codegen stuff noone understands to make it work. Replace most code testing explicitly for unit 0 and 1 with loops instead of adding test for unit 2, smaller/more readable code at the cost of maybe some slight performance hit. (Code provided by Andreas Stenglein, some adjustments by me.) --- src/mesa/drivers/dri/radeon/radeon_context.c | 23 ++-- src/mesa/drivers/dri/radeon/radeon_context.h | 37 ++++--- src/mesa/drivers/dri/radeon/radeon_maos.c | 2 +- src/mesa/drivers/dri/radeon/radeon_maos_arrays.c | 92 ++++++---------- src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h | 2 + src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 134 +++++++++++++++++------ src/mesa/drivers/dri/radeon/radeon_screen.c | 3 +- src/mesa/drivers/dri/radeon/radeon_state.c | 25 ++--- src/mesa/drivers/dri/radeon/radeon_state_init.c | 18 ++- src/mesa/drivers/dri/radeon/radeon_swtcl.c | 2 +- src/mesa/drivers/dri/radeon/radeon_tcl.h | 3 +- src/mesa/drivers/dri/radeon/radeon_texstate.c | 28 +---- src/mesa/drivers/dri/radeon/radeon_vtxfmt.c | 128 ++++++++++------------ src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c | 14 ++- src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c | 4 + src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c | 5 +- src/mesa/drivers/dri/radeon/radeon_vtxtmp_x86.S | 16 +-- 17 files changed, 285 insertions(+), 251 deletions(-) diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index abb2c72e79c..9ab6e676780 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -69,7 +69,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define need_GL_EXT_secondary_color #include "extension_helper.h" -#define DRIVER_DATE "20050831" +#define DRIVER_DATE "20051008" #include "vblank.h" #include "utils.h" @@ -327,9 +327,10 @@ radeonCreateContext( const __GLcontextModes *glVisual, */ ctx = rmesa->glCtx; - ctx->Const.MaxTextureUnits = 2; - ctx->Const.MaxTextureImageUnits = 2; - ctx->Const.MaxTextureCoordUnits = 2; + ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache, + "texture_units"); + ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits; + ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits; driCalculateMaxTextureLevels( rmesa->texture_heaps, rmesa->nr_heaps, @@ -403,14 +404,12 @@ radeonCreateContext( const __GLcontextModes *glVisual, _tnl_allow_vertex_fog( ctx, GL_TRUE ); - _math_matrix_ctr( &rmesa->TexGenMatrix[0] ); - _math_matrix_ctr( &rmesa->TexGenMatrix[1] ); - _math_matrix_ctr( &rmesa->tmpmat[0] ); - _math_matrix_ctr( &rmesa->tmpmat[1] ); - _math_matrix_set_identity( &rmesa->TexGenMatrix[0] ); - _math_matrix_set_identity( &rmesa->TexGenMatrix[1] ); - _math_matrix_set_identity( &rmesa->tmpmat[0] ); - _math_matrix_set_identity( &rmesa->tmpmat[1] ); + for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) { + _math_matrix_ctr( &rmesa->TexGenMatrix[i] ); + _math_matrix_ctr( &rmesa->tmpmat[i] ); + _math_matrix_set_identity( &rmesa->TexGenMatrix[i] ); + _math_matrix_set_identity( &rmesa->tmpmat[i] ); + } driInitExtensions( ctx, card_extensions, GL_TRUE ); if (rmesa->glCtx->Mesa_DXTn) { diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 3bd8f6ebc68..09bb96861ee 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -122,11 +122,17 @@ struct radeon_stipple_state { GLuint mask[32]; }; +/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ +#define RADEON_ST_BIT(unit) \ +(unit == 0 ? RADEON_CP_VC_FRMT_ST0 : (RADEON_CP_VC_FRMT_ST1 >> 2) << (2 * unit)) +#define RADEON_Q_BIT(unit) \ +(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit)) #define TEX_0 0x1 #define TEX_1 0x2 -#define TEX_ALL 0x3 +#define TEX_2 0x4 +#define TEX_ALL 0x7 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; @@ -408,17 +414,17 @@ struct radeon_hw_state { struct radeon_state_atom vpt; struct radeon_state_atom tcl; struct radeon_state_atom msc; - struct radeon_state_atom tex[2]; + struct radeon_state_atom tex[3]; struct radeon_state_atom zbs; struct radeon_state_atom mtl; - struct radeon_state_atom mat[5]; + struct radeon_state_atom mat[6]; struct radeon_state_atom lit[8]; /* includes vec, scl commands */ struct radeon_state_atom ucp[6]; struct radeon_state_atom eye; /* eye pos */ struct radeon_state_atom grd; /* guard band clipping */ struct radeon_state_atom fog; struct radeon_state_atom glt; - struct radeon_state_atom txr[2]; /* for NPOT */ + struct radeon_state_atom txr[3]; /* for NPOT */ int max_state_size; /* Number of bytes necessary for a full state emit. */ GLboolean is_dirty, all_dirty; @@ -646,30 +652,29 @@ struct radeon_prim { GLuint prim; }; +/* A maximum total of 20 elements per vertex: 3 floats for position, 3 + * floats for normal, 4 floats for color, 4 bytes for secondary color, + * 3 floats for each texture unit (9 floats total). + * + * The position data is never actually stored here, so 3 elements could be + * trimmed out of the buffer. This number is only valid for vtxfmt! + */ +#define RADEON_MAX_VERTEX_SIZE 20 + struct radeon_vbinfo { GLint counter, initial_counter; GLint *dmaptr; void (*notify)( void ); GLint vertex_size; - /* A maximum total of 15 elements per vertex: 3 floats for position, 3 - * floats for normal, 4 floats for color, 4 bytes for secondary color, - * 2 floats for each texture unit (4 floats total). - * - * As soon as the 3rd TMU is supported or cube maps (or 3D textures) are - * supported, this value will grow. - * - * The position data is never actually stored here, so 3 elements could be - * trimmed out of the buffer. - */ - union { float f; int i; radeon_color_t color; } vertex[15]; + union { float f; int i; radeon_color_t color; } vertex[RADEON_MAX_VERTEX_SIZE]; GLfloat *normalptr; GLfloat *floatcolorptr; radeon_color_t *colorptr; GLfloat *floatspecptr; radeon_color_t *specptr; - GLfloat *texcoordptr[2]; + GLfloat *texcoordptr[4]; /* 3 (TMU) + 1 for radeon_vtxfmt_c.c when GL_TEXTURE3 */ GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */ GLuint primflags; diff --git a/src/mesa/drivers/dri/radeon/radeon_maos.c b/src/mesa/drivers/dri/radeon/radeon_maos.c index c62edd715c7..ea1e8934de9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos.c @@ -4,7 +4,7 @@ * Otherwise, must use verts. */ #include "radeon_context.h" -#define RADEON_MAOS_VERTS 1 +#define RADEON_MAOS_VERTS 0 #if (RADEON_MAOS_VERTS) || (RADEON_OLD_PACKETS) #include "radeon_maos_verts.c" #else diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c index 5aa77b8afaa..1602464011a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c @@ -443,7 +443,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) GLuint nr = 0; GLuint vfmt = 0; GLuint count = VB->Count; - GLuint vtx; + GLuint vtx, unit; #if 0 if (RADEON_DEBUG & DEBUG_VERTS) @@ -526,58 +526,36 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) } vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & - ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1)); - - if (inputs & VERT_BIT_TEX0) { - if (!rmesa->tcl.tex[0].buf) - emit_tex_vector( ctx, - &(rmesa->tcl.tex[0]), - (char *)VB->TexCoordPtr[0]->data, - VB->TexCoordPtr[0]->size, - VB->TexCoordPtr[0]->stride, - count ); - - vfmt |= RADEON_CP_VC_FRMT_ST0; - /* assume we need the 3rd coord if texgen is active for r/q OR at least 3 - coords are submitted. This may not be 100% correct */ - if (VB->TexCoordPtr[0]->size >= 3) { - vtx |= RADEON_TCL_VTX_Q0; - vfmt |= RADEON_CP_VC_FRMT_Q0; + ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1|RADEON_TCL_VTX_Q2)); + + for (unit = 0; unit < ctx->Const.MaxTextureUnits; unit++) { + if (inputs & VERT_BIT_TEX(unit)) { + if (!rmesa->tcl.tex[unit].buf) + emit_tex_vector( ctx, + &(rmesa->tcl.tex[unit]), + (char *)VB->TexCoordPtr[unit]->data, + VB->TexCoordPtr[unit]->size, + VB->TexCoordPtr[unit]->stride, + count ); + + vfmt |= RADEON_ST_BIT(unit); + /* assume we need the 3rd coord if texgen is active for r/q OR at least + 3 coords are submitted. This may not be 100% correct */ + if (VB->TexCoordPtr[unit]->size >= 3) { + /* tcl_vtx and vc_frmt values are identical */ + vtx |= RADEON_Q_BIT(unit); + vfmt |= RADEON_Q_BIT(unit); + } + if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) + vtx |= RADEON_Q_BIT(unit); + else if (VB->TexCoordPtr[unit]->size >= 3) { + GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3); + if (((rmesa->NeedTexMatrix >> unit) & 1) && + (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) + radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; + } + component[nr++] = &rmesa->tcl.tex[unit]; } - if ( (ctx->Texture.Unit[0].TexGenEnabled & (R_BIT | Q_BIT)) ) - vtx |= RADEON_TCL_VTX_Q0; - else if (VB->TexCoordPtr[0]->size >= 3) { - GLuint swaptexmatcol = (VB->TexCoordPtr[0]->size - 3); - if ((rmesa->NeedTexMatrix & 1) && - (swaptexmatcol != (rmesa->TexMatColSwap & 1))) - radeonUploadTexMatrix( rmesa, 0, swaptexmatcol ) ; - } - component[nr++] = &rmesa->tcl.tex[0]; - } - - if (inputs & VERT_BIT_TEX1) { - if (!rmesa->tcl.tex[1].buf) - emit_tex_vector( ctx, - &(rmesa->tcl.tex[1]), - (char *)VB->TexCoordPtr[1]->data, - VB->TexCoordPtr[1]->size, - VB->TexCoordPtr[1]->stride, - count ); - - vfmt |= RADEON_CP_VC_FRMT_ST1; - if (VB->TexCoordPtr[1]->size >= 3) { - vtx |= RADEON_TCL_VTX_Q1; - vfmt |= RADEON_CP_VC_FRMT_Q1; - } - if ( (ctx->Texture.Unit[1].TexGenEnabled & (R_BIT | Q_BIT)) ) - vtx |= RADEON_TCL_VTX_Q1; - else if (VB->TexCoordPtr[1]->size >= 3) { - GLuint swaptexmatcol = (VB->TexCoordPtr[1]->size - 3); - if (((rmesa->NeedTexMatrix >> 1) & 1) && - (swaptexmatcol != ((rmesa->TexMatColSwap >> 1) & 1))) - radeonUploadTexMatrix( rmesa, 1, swaptexmatcol ) ; - } - component[nr++] = &rmesa->tcl.tex[1]; } if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) { @@ -593,6 +571,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) { radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); + GLuint unit; #if 0 if (RADEON_DEBUG & DEBUG_VERTS) @@ -611,9 +590,8 @@ void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs ) if (newinputs & VERT_BIT_COLOR1) radeonReleaseDmaRegion( rmesa, &rmesa->tcl.spec, __FUNCTION__ ); - if (newinputs & VERT_BIT_TEX0) - radeonReleaseDmaRegion( rmesa, &rmesa->tcl.tex[0], __FUNCTION__ ); - - if (newinputs & VERT_BIT_TEX1) - radeonReleaseDmaRegion( rmesa, &rmesa->tcl.tex[1], __FUNCTION__ ); + for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { + if (newinputs & VERT_BIT_TEX(unit)) + radeonReleaseDmaRegion( rmesa, &rmesa->tcl.tex[unit], __FUNCTION__ ); + } } diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h b/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h index fc31aff47aa..265d061b369 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h +++ b/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h @@ -255,6 +255,7 @@ static void TAG(emit)( GLcontext *ctx, if (DO_TEX2) { v[0].ui = tc2[0][0]; v[1].ui = tc2[0][1]; + if (TCL_DEBUG) fprintf(stderr, "t2: %.2f %.2f ", v[0].f, v[1].f); if (DO_PTEX) { if (fill_tex & (1<<2)) v[2].f = 1.0; @@ -262,6 +263,7 @@ static void TAG(emit)( GLcontext *ctx, v[2].ui = tc2[0][2]; else v[2].ui = tc2[0][3]; + if (TCL_DEBUG) fprintf(stderr, "%.2f ", v[2].f); v += 3; } else diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index 3d004adda68..57aa90321cf 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -51,7 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_maos.h" -#define RADEON_TCL_MAX_SETUP 13 +#define RADEON_TCL_MAX_SETUP 19 union emit_union { float f; GLuint ui; radeon_color_t rgba; }; @@ -67,10 +67,10 @@ static struct { #define DO_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC) #define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0) #define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1) +#define DO_TEX2 (IND & RADEON_CP_VC_FRMT_ST2) #define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0) #define DO_NORM (IND & RADEON_CP_VC_FRMT_N0) -#define DO_TEX2 0 #define DO_TEX3 0 #define GET_TEXSOURCE(n) n @@ -202,6 +202,77 @@ static struct { #define TAG(x) x##_w_rgba_spec_stq_stq_n #include "radeon_maos_vbtmp.h" +#define IDX 13 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_ST2) +#define TAG(x) x##_rgba_st_st_st +#include "radeon_maos_vbtmp.h" + +#define IDX 14 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_PKSPEC| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_ST2) +#define TAG(x) x##_rgba_spec_st_st_st +#include "radeon_maos_vbtmp.h" + +#define IDX 15 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_ST2| \ + RADEON_CP_VC_FRMT_N0) +#define TAG(x) x##_st_st_st_n +#include "radeon_maos_vbtmp.h" + +#define IDX 16 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_PKSPEC| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_ST2| \ + RADEON_CP_VC_FRMT_N0) +#define TAG(x) x##_rgba_spec_st_st_st_n +#include "radeon_maos_vbtmp.h" + +#define IDX 17 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_Q0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_Q1| \ + RADEON_CP_VC_FRMT_ST2| \ + RADEON_CP_VC_FRMT_Q2) +#define TAG(x) x##_rgba_stq_stq_stq +#include "radeon_maos_vbtmp.h" + +#define IDX 18 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_W0| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_PKSPEC| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_Q0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_Q1| \ + RADEON_CP_VC_FRMT_ST2| \ + RADEON_CP_VC_FRMT_Q2| \ + RADEON_CP_VC_FRMT_N0) +#define TAG(x) x##_w_rgba_spec_stq_stq_stq_n +#include "radeon_maos_vbtmp.h" @@ -226,6 +297,12 @@ static void init_tcl_verts( void ) init_rgba_stq(); init_rgba_stq_stq(); init_w_rgba_spec_stq_stq_n(); + init_rgba_st_st_st(); + init_rgba_spec_st_st_st(); + init_st_st_st_n(); + init_rgba_spec_st_st_st_n(); + init_rgba_stq_stq_stq(); + init_w_rgba_spec_stq_stq_stq_n(); } @@ -234,8 +311,9 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) radeonContextPtr rmesa = RADEON_CONTEXT(ctx); struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb; GLuint req = 0; + GLuint unit; GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & - ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1)); + ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1|RADEON_TCL_VTX_Q2)); int i; static int firsttime = 1; @@ -263,39 +341,23 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) req |= RADEON_CP_VC_FRMT_PKSPEC; } - if (inputs & VERT_BIT_TEX0) { - req |= RADEON_CP_VC_FRMT_ST0; - /* assume we need the 3rd coord if texgen is active for r/q OR at least 3 - coords are submitted. This may not be 100% correct */ - if (VB->TexCoordPtr[0]->size >= 3) { - req |= RADEON_CP_VC_FRMT_Q0; - vtx |= RADEON_TCL_VTX_Q0; - } - if ( (ctx->Texture.Unit[0].TexGenEnabled & (R_BIT | Q_BIT)) ) - vtx |= RADEON_TCL_VTX_Q0; - else if (VB->TexCoordPtr[0]->size >= 3) { - GLuint swaptexmatcol = (VB->TexCoordPtr[0]->size - 3); - if ((rmesa->NeedTexMatrix & 1) && - (swaptexmatcol != (rmesa->TexMatColSwap & 1))) - radeonUploadTexMatrix( rmesa, 0, swaptexmatcol ) ; - } - } - - - if (inputs & VERT_BIT_TEX1) { - req |= RADEON_CP_VC_FRMT_ST1; - - if (VB->TexCoordPtr[1]->size >= 3) { - req |= RADEON_CP_VC_FRMT_Q1; - vtx |= RADEON_TCL_VTX_Q1; - } - if ( (ctx->Texture.Unit[1].TexGenEnabled & (R_BIT | Q_BIT)) ) - vtx |= RADEON_TCL_VTX_Q1; - else if (VB->TexCoordPtr[1]->size >= 3) { - GLuint swaptexmatcol = (VB->TexCoordPtr[1]->size - 3); - if (((rmesa->NeedTexMatrix >> 1) & 1) && - (swaptexmatcol != ((rmesa->TexMatColSwap >> 1) & 1))) - radeonUploadTexMatrix( rmesa, 1, swaptexmatcol ) ; + for (unit = 0; unit < ctx->Const.MaxTextureUnits; unit++) { + if (inputs & VERT_BIT_TEX(unit)) { + req |= RADEON_ST_BIT(unit); + /* assume we need the 3rd coord if texgen is active for r/q OR at least + 3 coords are submitted. This may not be 100% correct */ + if (VB->TexCoordPtr[unit]->size >= 3) { + req |= RADEON_Q_BIT(unit); + vtx |= RADEON_Q_BIT(unit); + } + if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) + vtx |= RADEON_Q_BIT(unit); + else if (VB->TexCoordPtr[unit]->size >= 3) { + GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3); + if (((rmesa->NeedTexMatrix >> unit) & 1) && + (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) + radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; + } } } diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 9f25de44e2a..c79f406f68a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -65,6 +65,7 @@ DRI_CONF_BEGIN DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) + DRI_CONF_MAX_TEXTURE_UNITS(2,2,3) DRI_CONF_HYPERZ(false) DRI_CONF_SECTION_END DRI_CONF_SECTION_QUALITY @@ -81,7 +82,7 @@ DRI_CONF_BEGIN DRI_CONF_NO_RAST(false) DRI_CONF_SECTION_END DRI_CONF_END; -static const GLuint __driNConfigOptions = 13; +static const GLuint __driNConfigOptions = 14; extern const struct dri_extension card_extensions[]; diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 6457fcac5de..a79fefee502 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -2145,7 +2145,7 @@ static void update_texturematrix( GLcontext *ctx ) rmesa->NeedTexMatrix = 0; rmesa->TexMatColSwap = 0; - for (unit = 0 ; unit < 2; unit++) { + for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { if (ctx->Texture.Unit[unit]._ReallyEnabled) { GLboolean needMatrix = GL_FALSE; if (ctx->TextureMatrixStack[unit].Top->type != MATRIX_IDENTITY) { @@ -2189,18 +2189,17 @@ static void update_texturematrix( GLcontext *ctx ) tpc = (texMatEnabled | rmesa->TexGenEnabled); - vs &= ~((0xf << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | - (0xf << RADEON_TCL_TEX_1_OUTPUT_SHIFT)); - - if (tpc & RADEON_TEXGEN_TEXMAT_0_ENABLE) - vs |= RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT; - else - vs |= RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT; - - if (tpc & RADEON_TEXGEN_TEXMAT_1_ENABLE) - vs |= RADEON_TCL_TEX_COMPUTED_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT; - else - vs |= RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT; + /* TCL_TEX_COMPUTED_x is TCL_TEX_INPUT_x | 0x8 */ + vs &= ~((RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) | + (RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) | + (RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_2_OUTPUT_SHIFT)); + + vs |= (((tpc & RADEON_TEXGEN_TEXMAT_0_ENABLE) << + (RADEON_TCL_TEX_0_OUTPUT_SHIFT + 3)) | + ((tpc & RADEON_TEXGEN_TEXMAT_1_ENABLE) << + (RADEON_TCL_TEX_1_OUTPUT_SHIFT + 2)) | + ((tpc & RADEON_TEXGEN_TEXMAT_2_ENABLE) << + (RADEON_TCL_TEX_2_OUTPUT_SHIFT + 1))); if (tpc != rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] || vs != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL]) { diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index be3635a3809..7e7dc0f7823 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -115,10 +115,12 @@ static GLboolean check_##NM( GLcontext *ctx ) \ CHECK( always, GL_TRUE ) CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled ) CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled ) +CHECK( tex2, ctx->Texture.Unit[2]._ReallyEnabled ) CHECK( fog, ctx->Fog.Enabled ) TCL_CHECK( tcl, GL_TRUE ) TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled ) TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled ) +TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled ) TCL_CHECK( tcl_lighting, ctx->Light.Enabled ) TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled ) TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled ) @@ -139,6 +141,7 @@ TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled ) CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT)) CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT)) +CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT)) @@ -229,11 +232,13 @@ void radeonInitState( radeonContextPtr rmesa ) ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 ); ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 ); ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 ); + ALLOC_STATE( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0 ); ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 ); ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 ); ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 ); ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 ); ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 ); + ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 ); ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 ); ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 ); @@ -250,6 +255,7 @@ void radeonInitState( radeonContextPtr rmesa ) ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 ); ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 ); ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 ); + ALLOC_STATE( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0 ); radeonSetUpAtomList( rmesa ); @@ -269,12 +275,15 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0); rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1); rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1); + rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_2); + rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_2); rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR); rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); rmesa->hw.mtl.cmd[MTL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0); rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1); + rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_2); rmesa->hw.grd.cmd[GRD_CMD_0] = cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); rmesa->hw.fog.cmd[FOG_CMD_0] = @@ -284,7 +293,7 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.eye.cmd[EYE_CMD_0] = cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 ); - for (i = 0 ; i < 5; i++) { + for (i = 0 ; i < 6; i++) { rmesa->hw.mat[i].cmd[MAT_CMD_0] = cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16); } @@ -309,8 +318,8 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_CHROMA_FUNC_FAIL | RADEON_CHROMA_KEY_NEAREST | RADEON_SHADOW_FUNC_EQUAL | - RADEON_SHADOW_PASS_1 | - RADEON_RIGHT_HAND_CUBE_OGL); + RADEON_SHADOW_PASS_1 /*| + RADEON_RIGHT_HAND_CUBE_OGL */); rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX | RADEON_FOG_USE_DEPTH); @@ -505,7 +514,8 @@ void radeonInitState( radeonContextPtr rmesa ) rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) | (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) | - (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT)); + (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) | + (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT)); rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = (RADEON_UCP_IN_CLIP_SPACE | diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index 90456191878..7200f71ef6b 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -625,7 +625,7 @@ static void radeonResetLineStipple( GLcontext *ctx ); #define RADEON_TWOSIDE_BIT 0x01 #define RADEON_UNFILLED_BIT 0x02 -#define RADEON_MAX_TRIFUNC 0x08 +#define RADEON_MAX_TRIFUNC 0x04 static struct { diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.h b/src/mesa/drivers/dri/radeon/radeon_tcl.h index 263b803d625..062c9fbb543 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tcl.h +++ b/src/mesa/drivers/dri/radeon/radeon_tcl.h @@ -56,7 +56,8 @@ extern void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode ); #define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */ #define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */ -#define RADEON_MAX_TCL_VERTSIZE (15*4) +/* max maos_verts vertex format has a size of 18 floats */ +#define RADEON_MAX_TCL_VERTSIZE (18*4) #define TCL_FALLBACK( ctx, bit, mode ) radeonTclFallback( ctx, bit, mode ) diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index 56ec2ae398d..fe5445bf626 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -921,10 +921,7 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit ) this from way too many places, would be much easier if we could leave tcl q coord always enabled as on r200) */ RADEON_STATECHANGE( rmesa, tcl ); - if (unit == 0) - rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_Q0; - else - rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_Q1; + rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_Q_BIT(unit); } switch (texUnit->GenModeS) { @@ -997,19 +994,8 @@ static void disable_tex( GLcontext *ctx, int unit ) ~((RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit); RADEON_STATECHANGE( rmesa, tcl ); - switch (unit) { - case 0: - rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_TCL_VTX_ST0 | - RADEON_TCL_VTX_Q0); - break; - case 1: - rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_TCL_VTX_ST1 | - RADEON_TCL_VTX_Q1); - break; - default: - break; - } - + rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) | + RADEON_Q_BIT(unit)); if (rmesa->TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_ST0; - else - rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_ST1; + rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit); rmesa->recheck_texgen[unit] = GL_TRUE; } @@ -1199,7 +1182,8 @@ void radeonUpdateTextureState( GLcontext *ctx ) GLboolean ok; ok = (radeonUpdateTextureUnit( ctx, 0 ) && - radeonUpdateTextureUnit( ctx, 1 )); + radeonUpdateTextureUnit( ctx, 1 ) && + radeonUpdateTextureUnit( ctx, 2 )); FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, !ok ); diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c b/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c index c5ea51cea9d..e554aeb3300 100644 --- a/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c +++ b/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c @@ -57,6 +57,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_swtcl.h" #include "radeon_vtxfmt.h" +#define VERT_ATTRIB_TEX(u) (VERT_ATTRIB_TEX0 + (u)) + #include "dispatch.h" static void radeonVtxfmtFlushVertices( GLcontext *, GLuint ); @@ -102,6 +104,7 @@ static void count_funcs( radeonContextPtr rmesa ) void radeon_copy_to_current( GLcontext *ctx ) { + GLuint unit; radeonContextPtr rmesa = RADEON_CONTEXT(ctx); assert(ctx->Driver.NeedFlush & FLUSH_UPDATE_CURRENT); @@ -134,18 +137,13 @@ void radeon_copy_to_current( GLcontext *ctx ) ctx->Current.Attrib[VERT_ATTRIB_COLOR1][2] = UBYTE_TO_FLOAT( rmesa->vb.specptr->blue ); } - if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_ST0) { - ctx->Current.Attrib[VERT_ATTRIB_TEX0][0] = rmesa->vb.texcoordptr[0][0]; - ctx->Current.Attrib[VERT_ATTRIB_TEX0][1] = rmesa->vb.texcoordptr[0][1]; - ctx->Current.Attrib[VERT_ATTRIB_TEX0][2] = 0.0F; - ctx->Current.Attrib[VERT_ATTRIB_TEX0][3] = 1.0F; - } - - if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_ST1) { - ctx->Current.Attrib[VERT_ATTRIB_TEX1][0] = rmesa->vb.texcoordptr[1][0]; - ctx->Current.Attrib[VERT_ATTRIB_TEX1][1] = rmesa->vb.texcoordptr[1][1]; - ctx->Current.Attrib[VERT_ATTRIB_TEX1][2] = 0.0F; - ctx->Current.Attrib[VERT_ATTRIB_TEX1][3] = 1.0F; + for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { + if (rmesa->vb.vertex_format & RADEON_ST_BIT(unit)) { + ctx->Current.Attrib[VERT_ATTRIB_TEX(unit)][0] = rmesa->vb.texcoordptr[unit][0]; + ctx->Current.Attrib[VERT_ATTRIB_TEX(unit)][1] = rmesa->vb.texcoordptr[unit][1]; + ctx->Current.Attrib[VERT_ATTRIB_TEX(unit)][2] = 0.0F; + ctx->Current.Attrib[VERT_ATTRIB_TEX(unit)][3] = 1.0F; + } } ctx->Driver.NeedFlush &= ~FLUSH_UPDATE_CURRENT; @@ -264,7 +262,7 @@ static void copy_vertex( radeonContextPtr rmesa, GLuint n, GLfloat *dst ) * memory. Could also use the counter/notify mechanism to populate * tmp on the fly as vertices are generated. */ -static GLuint copy_dma_verts( radeonContextPtr rmesa, GLfloat (*tmp)[15] ) +static GLuint copy_dma_verts( radeonContextPtr rmesa, GLfloat (*tmp)[RADEON_MAX_VERTEX_SIZE] ) { GLuint ovf, i; GLuint nr = (rmesa->vb.initial_counter - rmesa->vb.counter) - rmesa->vb.primlist[rmesa->vb.nrprims].start; @@ -356,11 +354,12 @@ static void VFMT_FALLBACK( const char *caller ) { GET_CURRENT_CONTEXT(ctx); radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - GLfloat tmp[3][15]; + GLfloat tmp[3][RADEON_MAX_VERTEX_SIZE]; GLuint i, prim; GLuint ind = rmesa->vb.vertex_format; GLuint nrverts; GLfloat alpha = 1.0; + GLuint unit; if (RADEON_DEBUG & (DEBUG_FALLBACKS|DEBUG_VFMT)) fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); @@ -423,14 +422,11 @@ static void VFMT_FALLBACK( const char *caller ) offset++; } - if (ind & RADEON_CP_VC_FRMT_ST0) { - CALL_TexCoord2fv(GET_DISPATCH(), (&tmp[i][offset])); - offset += 2; - } - - if (ind & RADEON_CP_VC_FRMT_ST1) { - CALL_MultiTexCoord2fvARB(GET_DISPATCH(), (GL_TEXTURE1_ARB, &tmp[i][offset])); - offset += 2; + for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { + if (ind & RADEON_ST_BIT(unit)) { + CALL_MultiTexCoord2fvARB(GET_DISPATCH(), ((GL_TEXTURE0 + unit), &tmp[i][offset])); + offset += 2; + } } CALL_Vertex3fv(GET_DISPATCH(), (&tmp[i][0])); } @@ -441,7 +437,8 @@ static void VFMT_FALLBACK( const char *caller ) CALL_Normal3fv(GET_DISPATCH(), (rmesa->vb.normalptr)); if (ind & RADEON_CP_VC_FRMT_PKCOLOR) - CALL_Color4ub(GET_DISPATCH(), (rmesa->vb.colorptr->red, rmesa->vb.colorptr->green, rmesa->vb.colorptr->blue, rmesa->vb.colorptr->alpha)); + CALL_Color4ub(GET_DISPATCH(), (rmesa->vb.colorptr->red, rmesa->vb.colorptr->green, + rmesa->vb.colorptr->blue, rmesa->vb.colorptr->alpha)); else if (ind & RADEON_CP_VC_FRMT_FPALPHA) CALL_Color4fv(GET_DISPATCH(), (rmesa->vb.floatcolorptr)); else if (ind & RADEON_CP_VC_FRMT_FPCOLOR) { @@ -455,13 +452,16 @@ static void VFMT_FALLBACK( const char *caller ) } if (ind & RADEON_CP_VC_FRMT_PKSPEC) - CALL_SecondaryColor3ubEXT(GET_DISPATCH(), (rmesa->vb.specptr->red, rmesa->vb.specptr->green, rmesa->vb.specptr->blue)); - - if (ind & RADEON_CP_VC_FRMT_ST0) - CALL_TexCoord2fv(GET_DISPATCH(), (rmesa->vb.texcoordptr[0])); - - if (ind & RADEON_CP_VC_FRMT_ST1) - CALL_MultiTexCoord2fvARB(GET_DISPATCH(), (GL_TEXTURE1_ARB, rmesa->vb.texcoordptr[1])); + CALL_SecondaryColor3ubEXT(GET_DISPATCH(), (rmesa->vb.specptr->red, + rmesa->vb.specptr->green, + rmesa->vb.specptr->blue)); + + for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { + if (ind & RADEON_ST_BIT(unit)) { + CALL_MultiTexCoord2fvARB(GET_DISPATCH(), ((GL_TEXTURE0 + unit), + rmesa->vb.texcoordptr[unit])); + } + } } @@ -470,7 +470,7 @@ static void wrap_buffer( void ) { GET_CURRENT_CONTEXT(ctx); radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - GLfloat tmp[3][15]; + GLfloat tmp[3][RADEON_MAX_VERTEX_SIZE]; GLuint i, nrverts; if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_PRIMS)) @@ -547,6 +547,7 @@ static GLboolean check_vtx_fmt( GLcontext *ctx ) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); GLuint ind = RADEON_CP_VC_FRMT_Z; + GLuint unit; if (rmesa->TclFallback || rmesa->vb.fell_back || ctx->CompileFlag) return GL_FALSE; @@ -581,35 +582,20 @@ static GLboolean check_vtx_fmt( GLcontext *ctx ) } } - if (ctx->Texture.Unit[0]._ReallyEnabled) { - if (ctx->Texture.Unit[0].TexGenEnabled) { - if (rmesa->TexGenNeedNormals[0]) { - ind |= RADEON_CP_VC_FRMT_N0; - } - } else { - if (ctx->Current.Attrib[VERT_ATTRIB_TEX0][2] != 0.0F || - ctx->Current.Attrib[VERT_ATTRIB_TEX0][3] != 1.0) { - if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_FALLBACKS)) - fprintf(stderr, "%s: rq0\n", __FUNCTION__); - return GL_FALSE; - } - ind |= RADEON_CP_VC_FRMT_ST0; - } - } - - if (ctx->Texture.Unit[1]._ReallyEnabled) { - if (ctx->Texture.Unit[1].TexGenEnabled) { - if (rmesa->TexGenNeedNormals[1]) { - ind |= RADEON_CP_VC_FRMT_N0; - } - } else { - if (ctx->Current.Attrib[VERT_ATTRIB_TEX1][2] != 0.0F || - ctx->Current.Attrib[VERT_ATTRIB_TEX1][3] != 1.0) { - if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_FALLBACKS)) - fprintf(stderr, "%s: rq1\n", __FUNCTION__); - return GL_FALSE; + for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { + if (ctx->Texture.Unit[unit]._ReallyEnabled) { + if (ctx->Texture.Unit[unit].TexGenEnabled) { + if (rmesa->TexGenNeedNormals[unit]) { + ind |= RADEON_CP_VC_FRMT_N0; + } + } else { + if (ctx->Current.Attrib[VERT_ATTRIB_TEX(unit)][3] != 1.0) { + if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_FALLBACKS)) + fprintf(stderr, "%s: q%u\n", __FUNCTION__, unit); + return GL_FALSE; + } + ind |= RADEON_ST_BIT(unit); } - ind |= RADEON_CP_VC_FRMT_ST1; } } @@ -628,6 +614,8 @@ static GLboolean check_vtx_fmt( GLcontext *ctx ) rmesa->vb.floatspecptr = ctx->Current.Attrib[VERT_ATTRIB_COLOR1]; rmesa->vb.texcoordptr[0] = ctx->Current.Attrib[VERT_ATTRIB_TEX0]; rmesa->vb.texcoordptr[1] = ctx->Current.Attrib[VERT_ATTRIB_TEX1]; + rmesa->vb.texcoordptr[2] = ctx->Current.Attrib[VERT_ATTRIB_TEX2]; + rmesa->vb.texcoordptr[3] = ctx->Current.Attrib[VERT_ATTRIB_TEX0]; /* dummy */ /* Run through and initialize the vertex components in the order * the hardware understands: @@ -671,19 +659,14 @@ static GLboolean check_vtx_fmt( GLcontext *ctx ) UNCLAMPED_FLOAT_TO_CHAN( rmesa->vb.specptr->blue, ctx->Current.Attrib[VERT_ATTRIB_COLOR1][2] ); } - if (ind & RADEON_CP_VC_FRMT_ST0) { - rmesa->vb.texcoordptr[0] = &rmesa->vb.vertex[rmesa->vb.vertex_size].f; - rmesa->vb.vertex_size += 2; - rmesa->vb.texcoordptr[0][0] = ctx->Current.Attrib[VERT_ATTRIB_TEX0][0]; - rmesa->vb.texcoordptr[0][1] = ctx->Current.Attrib[VERT_ATTRIB_TEX0][1]; - } - - if (ind & RADEON_CP_VC_FRMT_ST1) { - rmesa->vb.texcoordptr[1] = &rmesa->vb.vertex[rmesa->vb.vertex_size].f; - rmesa->vb.vertex_size += 2; - rmesa->vb.texcoordptr[1][0] = ctx->Current.Attrib[VERT_ATTRIB_TEX1][0]; - rmesa->vb.texcoordptr[1][1] = ctx->Current.Attrib[VERT_ATTRIB_TEX1][1]; - } + for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { + if (ind & RADEON_ST_BIT(unit)) { + rmesa->vb.texcoordptr[unit] = &rmesa->vb.vertex[rmesa->vb.vertex_size].f; + rmesa->vb.vertex_size += 2; + rmesa->vb.texcoordptr[unit][0] = ctx->Current.Attrib[VERT_ATTRIB_TEX(unit)][0]; + rmesa->vb.texcoordptr[unit][1] = ctx->Current.Attrib[VERT_ATTRIB_TEX(unit)][1]; + } + } if (rmesa->vb.installed_vertex_format != rmesa->vb.vertex_format) { if (RADEON_DEBUG & DEBUG_VFMT) @@ -813,6 +796,7 @@ static void radeon_Begin( GLenum mode ) /* Need to arrange to save vertices here? Or always copy from dma (yuk)? */ if (!rmesa->dma.flush) { +/* FIXME: what are these constants? */ if (rmesa->dma.current.ptr + 12*rmesa->vb.vertex_size*4 > rmesa->dma.current.end) { RADEON_NEWPRIM( rmesa ); diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c index 342b0b39c1b..aac029aa0e4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c +++ b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c @@ -563,7 +563,7 @@ static void radeon_MultiTexCoord1fARB( GLenum target, GLfloat s ) { GET_CURRENT_CONTEXT(ctx); radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - GLfloat *dest = rmesa->vb.texcoordptr[target & 1]; + GLfloat *dest = rmesa->vb.texcoordptr[target & 3]; dest[0] = s; dest[1] = 0; } @@ -572,7 +572,7 @@ static void radeon_MultiTexCoord1fvARB( GLenum target, const GLfloat *v ) { GET_CURRENT_CONTEXT(ctx); radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - GLfloat *dest = rmesa->vb.texcoordptr[target & 1]; + GLfloat *dest = rmesa->vb.texcoordptr[target & 3]; dest[0] = v[0]; dest[1] = 0; } @@ -581,7 +581,7 @@ static void radeon_MultiTexCoord2fARB( GLenum target, GLfloat s, GLfloat t ) { GET_CURRENT_CONTEXT(ctx); radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - GLfloat *dest = rmesa->vb.texcoordptr[target & 1]; + GLfloat *dest = rmesa->vb.texcoordptr[target & 3]; dest[0] = s; dest[1] = t; } @@ -590,7 +590,7 @@ static void radeon_MultiTexCoord2fvARB( GLenum target, const GLfloat *v ) { GET_CURRENT_CONTEXT(ctx); radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - GLfloat *dest = rmesa->vb.texcoordptr[target & 1]; + GLfloat *dest = rmesa->vb.texcoordptr[target & 3]; dest[0] = v[0]; dest[1] = v[1]; } @@ -746,7 +746,8 @@ static void choose_##FN ARGS1 \ #define ACTIVE_ST0 RADEON_CP_VC_FRMT_ST0 #define ACTIVE_ST1 RADEON_CP_VC_FRMT_ST1 -#define ACTIVE_ST_ALL (RADEON_CP_VC_FRMT_ST1|RADEON_CP_VC_FRMT_ST0) +#define ACTIVE_ST2 RADEON_CP_VC_FRMT_ST2 +#define ACTIVE_ST_ALL (RADEON_CP_VC_FRMT_ST1|RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST2) /* Each codegen function should be able to be fully specified by a * subsetted version of rmesa->vb.vertex_format. @@ -756,7 +757,8 @@ static void choose_##FN ARGS1 \ #define MASK_SPEC (MASK_COLOR|ACTIVE_COLOR) #define MASK_ST0 (MASK_SPEC|ACTIVE_SPEC) #define MASK_ST1 (MASK_ST0|ACTIVE_ST0) -#define MASK_ST_ALL (MASK_ST1|ACTIVE_ST1) +#define MASK_ST2 (MASK_ST1|ACTIVE_ST1) +#define MASK_ST_ALL (MASK_ST2|ACTIVE_ST2) #define MASK_VERTEX (MASK_ST_ALL|ACTIVE_FPALPHA) diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c index cb5d8401169..0f0fc9e0653 100644 --- a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c +++ b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c @@ -170,6 +170,7 @@ static struct dynfn *radeon_makeSSETexCoord2f( GLcontext *ctx, int key ) __FUNCTION__, rmesa->vb.texcoordptr[0] ); } +#if 0 /* Temporarily disabled - probably needs adjustments for more than 2 tex units -rs */ static struct dynfn *radeon_makeSSEMultiTexCoord2fv( GLcontext *ctx, int key ) { struct dynfn *dfn = MALLOC_STRUCT( dynfn ); @@ -207,6 +208,7 @@ static struct dynfn *radeon_makeSSEMultiTexCoord2f( GLcontext *ctx, int key ) } return dfn; } +#endif void radeonInitSSECodegen( struct dfn_generators *gen ) { @@ -217,8 +219,10 @@ void radeonInitSSECodegen( struct dfn_generators *gen ) gen->Color3f = (void *) radeon_makeSSEColor3f; gen->TexCoord2fv = (void *) radeon_makeSSETexCoord2fv; gen->TexCoord2f = (void *) radeon_makeSSETexCoord2f; +#if 0 /* Temporarily disabled - probably needs adjustments for more than 2 tex units -rs */ gen->MultiTexCoord2fvARB = (void *) radeon_makeSSEMultiTexCoord2fv; gen->MultiTexCoord2fARB = (void *) radeon_makeSSEMultiTexCoord2f; +#endif } } diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c index d1cf1979f1c..529e79065e9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c +++ b/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c @@ -351,6 +351,7 @@ struct dynfn *radeon_makeX86TexCoord2f( GLcontext *ctx, int key ) __FUNCTION__, rmesa->vb.texcoordptr[0] ); } +#if 0 /* Temporarily disabled - probably needs adjustments for more than 2 tex units -rs */ struct dynfn *radeon_makeX86MultiTexCoord2fvARB( GLcontext *ctx, int key ) { struct dynfn *dfn = MALLOC_STRUCT( dynfn ); @@ -395,7 +396,7 @@ struct dynfn *radeon_makeX86MultiTexCoord2fARB( GLcontext *ctx, } return dfn; } - +#endif void radeonInitX86Codegen( struct dfn_generators *gen ) { @@ -407,8 +408,10 @@ void radeonInitX86Codegen( struct dfn_generators *gen ) gen->Normal3fv = radeon_makeX86Normal3fv; gen->TexCoord2f = radeon_makeX86TexCoord2f; gen->TexCoord2fv = radeon_makeX86TexCoord2fv; +#if 0 /* Temporarily disabled - probably needs adjustments for more than 2 tex units -rs */ gen->MultiTexCoord2fARB = radeon_makeX86MultiTexCoord2fARB; gen->MultiTexCoord2fvARB = radeon_makeX86MultiTexCoord2fvARB; +#endif gen->Color3f = radeon_makeX86Color3f; gen->Color3fv = radeon_makeX86Color3fv; diff --git a/src/mesa/drivers/dri/radeon/radeon_vtxtmp_x86.S b/src/mesa/drivers/dri/radeon/radeon_vtxtmp_x86.S index 569d3b9b481..d2bb1d15192 100644 --- a/src/mesa/drivers/dri/radeon/radeon_vtxtmp_x86.S +++ b/src/mesa/drivers/dri/radeon/radeon_vtxtmp_x86.S @@ -338,7 +338,7 @@ GLOBL( _x86_Color4ub_ub_end ) GLOBL( _x86_MultiTexCoord2fv ) movl 4(%esp), %eax movl 8(%esp), %ecx - and $1, %eax + and $3, %eax movl (%ecx), %edx shl $3, %eax movl 4(%ecx), %ecx @@ -354,7 +354,7 @@ GLOBL( _x86_MultiTexCoord2fv_end ) GLOBL( _x86_MultiTexCoord2fv_2 ) movl 4(%esp,1), %eax movl 8(%esp,1), %ecx - and $0x1, %eax + and $3, %eax movl 0(,%eax,4), %edx movl (%ecx), %eax movl %eax, (%edx) @@ -370,7 +370,7 @@ GLOBL( _x86_MultiTexCoord2f ) movl 4(%esp), %eax movl 8(%esp), %edx movl 12(%esp), %ecx - and $1, %eax + and $3, %eax shl $3, %eax movl %edx, 0xdeadbeef(%eax) movl %ecx, 0xdeadbeef(%eax) @@ -384,7 +384,7 @@ GLOBL( _x86_MultiTexCoord2f_2 ) movl 4(%esp), %eax movl 8(%esp), %edx movl 12(%esp,1), %ecx - and $1,%eax + and $3,%eax movl 0(,%eax,4), %eax movl %edx, (%eax) movl %ecx, 4(%eax) @@ -450,7 +450,7 @@ GLOBL( _sse_Attribute2f_end ) GLOBL( _sse_MultiTexCoord2fv ) movl 4(%esp), %eax movl 8(%esp), %ecx - and $1, %eax + and $3, %eax movlps (%ecx), %xmm0 movlps %xmm0, 0xdeadbeef(,%eax,8) ret @@ -462,7 +462,7 @@ GLOBL( _sse_MultiTexCoord2fv_end ) GLOBL( _sse_MultiTexCoord2fv_2 ) movl 4(%esp), %eax movl 8(%esp), %ecx - and $0x1, %eax + and $3, %eax movl 0(,%eax,4), %edx movlps (%ecx), %xmm0 movlps %xmm0, (%edx) @@ -474,7 +474,7 @@ GLOBL( _sse_MultiTexCoord2fv_2_end ) */ GLOBL( _sse_MultiTexCoord2f ) movl 4(%esp), %eax - and $1, %eax + and $3, %eax movlps 8(%esp), %xmm0 movlps %xmm0, 0xdeadbeef(,%eax,8) ret @@ -486,7 +486,7 @@ GLOBL( _sse_MultiTexCoord2f_end ) GLOBL( _sse_MultiTexCoord2f_2 ) movl 4(%esp), %eax movlps 8(%esp), %xmm0 - and $1,%eax + and $3,%eax movl 0(,%eax,4), %eax movlps %xmm0, (%eax) ret -- 2.11.0