From 30f663b16f81d862256c7c71bc909d4588924d8c Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 12 Aug 2020 12:13:41 -0700 Subject: [PATCH] target/riscv: Only support little endian guests Signed-off-by: Alistair Francis Message-id: 93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com Message-Id: <93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com> --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 390ef781e4..5e50683c58 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -840,6 +840,8 @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) /* We only support 64-bit VSXL */ *val = set_field(*val, HSTATUS_VSXL, 2); #endif + /* We only support little endian */ + *val = set_field(*val, HSTATUS_VSBE, 0); return 0; } @@ -851,6 +853,9 @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); } #endif + if (get_field(val, HSTATUS_VSBE) != 0) { + qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); + } return 0; } -- 2.11.0