From 35ee7d28a69173ca0c11fb6b3271518bf4c5bff6 Mon Sep 17 00:00:00 2001
From: Silviu Baranga <silviu.baranga@arm.com>
Date: Wed, 18 Apr 2012 14:18:57 +0000
Subject: [PATCH] Added support for disassembling unpredictable swp/swpb ARM
 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrFormats.td                  |  1 +
 lib/Target/ARM/ARMInstrInfo.td                     |  4 ++--
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp    |  4 ++++
 test/MC/Disassembler/ARM/unpredictable-swp-arm.txt | 26 ++++++++++++++++++++++
 4 files changed, 33 insertions(+), 2 deletions(-)
 create mode 100644 test/MC/Disassembler/ARM/unpredictable-swp-arm.txt

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 1d38bcf9e84..f04926aaceb 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -532,6 +532,7 @@ class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
   let Inst{11-4} = 0b00001001;
   let Inst{3-0} = Rt2;
 
+  let Unpredictable{11-8} = 0b1111;
   let DecoderMethod = "DecodeSwap";
 }
 
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 807577e7696..1eb561d6901 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -4280,9 +4280,9 @@ def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
 
 // SWP/SWPB are deprecated in V6/V7.
 let mayLoad = 1, mayStore = 1 in {
-def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
+def SWP : AIswp<0, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr),
                 "swp", []>;
-def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
+def SWPB: AIswp<1, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr),
                 "swpb", []>;
 }
 
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 87a5f019d4a..912935db17a 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4310,6 +4310,10 @@ static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
 
   DecodeStatus S = MCDisassembler::Success;
+
+  if (Rt == Rn || Rn == Rt2)
+    S = MCDisassembler::SoftFail;
+
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
diff --git a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt
new file mode 100644
index 00000000000..64bb171bf81
--- /dev/null
+++ b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt
@@ -0,0 +1,26 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0x9f 0x10 0x03 0x01
+0x9f 0x10 0x03 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0xf0 0x03 0x01
+0x90 0xf0 0x03 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x1f 0x03 0x01
+0x90 0x1f 0x03 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x10 0x0f 0x01
+0x90 0x10 0x0f 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x10 0x01 0x01
+0x90 0x10 0x01 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x10 0x00 0x01
+0x90 0x10 0x00 0x01
+
-- 
2.11.0