From 376faf8a3b2ff497b1f1583ab4b23bc650711764 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Mon, 29 Jan 2018 15:22:18 -0800 Subject: [PATCH] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F. Since when it got introduced with commit '555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")' the support for Port F was wrong, because Port F bits are far from bits used for A to E. Since Port F is not used so far we don't need to propagate Fixes back there. v2: Reuse _SHIFT definition to avoid complicated duplication (DK). Cc: Dhinakaran Pandiyan Cc: Lucas De Marchi Cc: Manasi Navare Signed-off-by: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Link: https://patchwork.freedesktop.org/patch/msgid/20180129232223.766-5-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f66f48ffbdd6..596348632ed0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8759,10 +8759,12 @@ enum skl_power_gate { * CNL Clocks */ #define DPCLKA_CFGCR0 _MMIO(0x6C200) -#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10)) -#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2)) -#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2) -#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2)) +#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \ + (port)+10)) +#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \ + (port)*2) +#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) +#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) /* CNL PLL */ #define DPLL0_ENABLE 0x46010 -- 2.11.0