From 3795e0c7d5c8b81d4ae32129b860aaa169945ce3 Mon Sep 17 00:00:00 2001 From: Bard Liao Date: Mon, 12 Mar 2018 19:50:08 +0800 Subject: [PATCH] ASoC: rt5659: fix wrong control register for ADC2 power The control register for ADC L2 and R2 is RT5659_PWR_DIG_1 not RT5659_PWR_DIG_2. Signed-off-by: Zhong An Signed-off-by: Bard Liao Signed-off-by: Mark Brown --- sound/soc/codecs/rt5659.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/rt5659.c b/sound/soc/codecs/rt5659.c index 07e7757417bc..ebadc3da0aaf 100644 --- a/sound/soc/codecs/rt5659.c +++ b/sound/soc/codecs/rt5659.c @@ -2500,9 +2500,9 @@ static const struct snd_soc_dapm_widget rt5659_dapm_widgets[] = { RT5659_PWR_ADC_L1_BIT, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5659_PWR_DIG_1, RT5659_PWR_ADC_R1_BIT, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5659_PWR_DIG_2, + SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5659_PWR_DIG_1, RT5659_PWR_ADC_L2_BIT, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_2, + SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_1, RT5659_PWR_ADC_R2_BIT, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc_clk, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), -- 2.11.0