From 396e5e328ccae90acc6dff60f4957af8cc53c955 Mon Sep 17 00:00:00 2001 From: Saleem Abdulrasool Date: Wed, 2 Apr 2014 20:32:05 +0000 Subject: [PATCH] ARM: update subtarget information for Windows on ARM Update the subtarget information for Windows on ARM. This enables using the MC layer to target Windows on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205459 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/IR/DataLayout.cpp | 7 +++---- lib/Target/ARM/ARMISelLowering.cpp | 3 ++- lib/Target/ARM/ARMSubtarget.cpp | 6 ++++++ lib/Target/ARM/ARMSubtarget.h | 18 +++++++++------- lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp | 28 +++++++++++++++++++++++++ lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h | 13 ++++++++++++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 27 +++++++++++++++++++++--- test/CodeGen/ARM/Windows/aapcs.ll | 16 ++++++++++++++ test/CodeGen/ARM/Windows/hard-float.ll | 10 +++++++++ test/CodeGen/ARM/Windows/mangling.ll | 9 ++++++++ test/CodeGen/ARM/Windows/no-aeabi.ll | 10 +++++++++ test/CodeGen/ARM/Windows/no-arm-mode.ll | 5 +++++ test/CodeGen/ARM/Windows/no-ehabi.ll | 21 +++++++++++++++++++ 13 files changed, 157 insertions(+), 16 deletions(-) create mode 100644 test/CodeGen/ARM/Windows/aapcs.ll create mode 100644 test/CodeGen/ARM/Windows/hard-float.ll create mode 100644 test/CodeGen/ARM/Windows/mangling.ll create mode 100644 test/CodeGen/ARM/Windows/no-aeabi.ll create mode 100644 test/CodeGen/ARM/Windows/no-arm-mode.ll create mode 100644 test/CodeGen/ARM/Windows/no-ehabi.ll diff --git a/lib/IR/DataLayout.cpp b/lib/IR/DataLayout.cpp index 5654e15ae30..6c183872a3e 100644 --- a/lib/IR/DataLayout.cpp +++ b/lib/IR/DataLayout.cpp @@ -155,10 +155,9 @@ DataLayout::InvalidPointerElem = { 0U, 0U, 0U, ~0U }; const char *DataLayout::getManglingComponent(const Triple &T) { if (T.isOSBinFormatMachO()) return "-m:o"; - if (T.isOSBinFormatELF() || T.isArch64Bit()) - return "-m:e"; - assert(T.isOSBinFormatCOFF()); - return "-m:w"; + if (T.isOSWindows() && T.getArch() == Triple::x86 && T.isOSBinFormatCOFF()) + return "-m:w"; + return "-m:e"; } static const LayoutAlignElem DefaultAlignments[] = { diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 1778659b54f..0f43b324367 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -250,7 +250,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setLibcallName(RTLIB::SRL_I128, 0); setLibcallName(RTLIB::SRA_I128, 0); - if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO()) { + if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() && + !Subtarget->isTargetWindows()) { // Double-precision floating-point arithmetic helper functions // RTABI chapter 4.1.2, Table 2 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index d2f3b203fc6..5222c1b108b 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -212,6 +212,12 @@ void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { } } + // FIXME: this is invalid for WindowsCE + if (isTargetWindows()) { + TargetABI = ARM_ABI_AAPCS; + NoARM = true; + } + if (isAAPCS_ABI()) stackAlignment = 8; if (isTargetNaCl()) diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index 21fa83dff73..804f2386cae 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -317,14 +317,14 @@ public: const Triple &getTargetTriple() const { return TargetTriple; } - bool isTargetIOS() const { return TargetTriple.isiOS(); } bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } - bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } + bool isTargetIOS() const { return TargetTriple.isiOS(); } bool isTargetLinux() const { return TargetTriple.isOSLinux(); } - bool isTargetNetBSD() const { - return TargetTriple.getOS() == Triple::NetBSD; - } + bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } + bool isTargetNetBSD() const { return TargetTriple.getOS() == Triple::NetBSD; } + bool isTargetWindows() const { return TargetTriple.isOSWindows(); } + bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } @@ -338,7 +338,7 @@ public: bool isTargetAEABI() const { return (TargetTriple.getEnvironment() == Triple::EABI || TargetTriple.getEnvironment() == Triple::EABIHF) && - !isTargetDarwin(); + !isTargetDarwin() && !isTargetWindows(); } // ARM Targets that support EHABI exception handling standard @@ -349,12 +349,14 @@ public: TargetTriple.getEnvironment() == Triple::EABIHF || TargetTriple.getEnvironment() == Triple::GNUEABIHF || TargetTriple.getEnvironment() == Triple::Android) && - !isTargetDarwin(); + !isTargetDarwin() && !isTargetWindows(); } bool isTargetHardFloat() const { + // FIXME: this is invalid for WindowsCE return TargetTriple.getEnvironment() == Triple::GNUEABIHF || - TargetTriple.getEnvironment() == Triple::EABIHF; + TargetTriple.getEnvironment() == Triple::EABIHF || + isTargetWindows(); } bool isTargetAndroid() const { return TargetTriple.getEnvironment() == Triple::Android; diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp index 52e1fb9dd53..b7f96e08808 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp @@ -76,3 +76,31 @@ void ARMELFMCAsmInfo::setUseIntegratedAssembler(bool Value) { DwarfRegNumForCFI = true; } } + +void ARMCOFFMCAsmInfoMicrosoft::anchor() { } + +ARMCOFFMCAsmInfoMicrosoft::ARMCOFFMCAsmInfoMicrosoft() { + AlignmentIsInBytes = false; + + PrivateGlobalPrefix = "$M"; +} + +void ARMCOFFMCAsmInfoGNU::anchor() { } + +ARMCOFFMCAsmInfoGNU::ARMCOFFMCAsmInfoGNU() { + AlignmentIsInBytes = false; + + CommentString = "@"; + Code16Directive = ".code\t16"; + Code32Directive = ".code\t32"; + PrivateGlobalPrefix = ".L"; + + HasLEB128 = true; + SupportsDebugInformation = true; + ExceptionsType = ExceptionHandling::None; + UseParensForSymbolVariant = true; + + UseIntegratedAssembler = false; + DwarfRegNumForCFI = true; +} + diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h index be0295279c0..beaf6a40007 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h +++ b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h @@ -14,6 +14,7 @@ #ifndef LLVM_ARMTARGETASMINFO_H #define LLVM_ARMTARGETASMINFO_H +#include "llvm/MC/MCAsmInfoCOFF.h" #include "llvm/MC/MCAsmInfoDarwin.h" #include "llvm/MC/MCAsmInfoELF.h" @@ -33,6 +34,18 @@ namespace llvm { void setUseIntegratedAssembler(bool Value) override; }; + class ARMCOFFMCAsmInfoMicrosoft : public MCAsmInfoMicrosoft { + void anchor(); + public: + explicit ARMCOFFMCAsmInfoMicrosoft(); + }; + + class ARMCOFFMCAsmInfoGNU : public MCAsmInfoGNUCOFF { + void anchor(); + public: + explicit ARMCOFFMCAsmInfoGNU(); + }; + } // namespace llvm #endif diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 99e73a56f82..949a3d58377 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -218,10 +218,31 @@ static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { Triple TheTriple(TT); MCAsmInfo *MAI; - if (TheTriple.isOSBinFormatMachO()) + switch (TheTriple.getOS()) { + case llvm::Triple::Darwin: + case llvm::Triple::IOS: + case llvm::Triple::MacOSX: MAI = new ARMMCAsmInfoDarwin(TT); - else - MAI = new ARMELFMCAsmInfo(TT); + break; + case llvm::Triple::Win32: + switch (TheTriple.getEnvironment()) { + case llvm::Triple::Itanium: + MAI = new ARMCOFFMCAsmInfoGNU(); + break; + case llvm::Triple::MSVC: + MAI = new ARMCOFFMCAsmInfoMicrosoft(); + break; + default: + llvm_unreachable("invalid environment"); + } + break; + default: + if (TheTriple.isOSBinFormatMachO()) + MAI = new ARMMCAsmInfoDarwin(TT); + else + MAI = new ARMELFMCAsmInfo(TT); + break; + } unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(0, Reg, 0)); diff --git a/test/CodeGen/ARM/Windows/aapcs.ll b/test/CodeGen/ARM/Windows/aapcs.ll new file mode 100644 index 00000000000..3f9a09f8e7f --- /dev/null +++ b/test/CodeGen/ARM/Windows/aapcs.ll @@ -0,0 +1,16 @@ +; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s | FileCheck %s + +; AAPCS mandates an 8-byte stack alignment. The alloca is implicitly aligned, +; and no bic is required. + +declare void @callee(i8 *%i) + +define void @caller() { + %i = alloca i8, align 8 + call void @callee(i8* %i) + ret void +} + +; CHECK: sub sp, #8 +; CHECK-NOT: bic + diff --git a/test/CodeGen/ARM/Windows/hard-float.ll b/test/CodeGen/ARM/Windows/hard-float.ll new file mode 100644 index 00000000000..f7b7ec273ce --- /dev/null +++ b/test/CodeGen/ARM/Windows/hard-float.ll @@ -0,0 +1,10 @@ +; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s | FileCheck %s + +define float @function(float %f, float %g) nounwind { +entry: + %h = fadd float %f, %g + ret float %h +} + +; CHECK: vadd.f32 s0, s0, s1 + diff --git a/test/CodeGen/ARM/Windows/mangling.ll b/test/CodeGen/ARM/Windows/mangling.ll new file mode 100644 index 00000000000..ce1fe2ee7e1 --- /dev/null +++ b/test/CodeGen/ARM/Windows/mangling.ll @@ -0,0 +1,9 @@ +; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -o - %s | FileCheck %s + +define void @function() nounwind { +entry: + ret void +} + +; CHECK-LABEL: function + diff --git a/test/CodeGen/ARM/Windows/no-aeabi.ll b/test/CodeGen/ARM/Windows/no-aeabi.ll new file mode 100644 index 00000000000..4c6676f2df0 --- /dev/null +++ b/test/CodeGen/ARM/Windows/no-aeabi.ll @@ -0,0 +1,10 @@ +; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s | FileCheck %s + +define i32 @divide(i32 %i, i32 %j) nounwind { +entry: + %quotient = sdiv i32 %i, %j + ret i32 %quotient +} + +; CHECK-NOT: __aeabi_idiv + diff --git a/test/CodeGen/ARM/Windows/no-arm-mode.ll b/test/CodeGen/ARM/Windows/no-arm-mode.ll new file mode 100644 index 00000000000..6db031fc916 --- /dev/null +++ b/test/CodeGen/ARM/Windows/no-arm-mode.ll @@ -0,0 +1,5 @@ +; RUN: not llc -mtriple=armv7-windows-itanium -mcpu=cortex-a9 -o /dev/null %s 2>&1 \ +; RUN: | FileCheck %s + +; CHECK: does not support ARM mode execution + diff --git a/test/CodeGen/ARM/Windows/no-ehabi.ll b/test/CodeGen/ARM/Windows/no-ehabi.ll new file mode 100644 index 00000000000..4119b6da968 --- /dev/null +++ b/test/CodeGen/ARM/Windows/no-ehabi.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -o - %s | FileCheck %s + +declare void @callee(i32 %i) + +define i32 @caller(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, + i32 %p) { +entry: + %q = add nsw i32 %j, %i + %r = add nsw i32 %q, %k + %s = add nsw i32 %r, %l + call void @callee(i32 %s) + %t = add nsw i32 %n, %m + %u = add nsw i32 %t, %o + %v = add nsw i32 %u, %p + call void @callee(i32 %v) + %w = add nsw i32 %v, %s + ret i32 %w +} + +; CHECK-NOT: .save {{{.*}}} + -- 2.11.0