From 39befc6ca87809f13cf33bb6aec5ddc36c560d92 Mon Sep 17 00:00:00 2001 From: Pawel Bylica Date: Mon, 22 Jun 2015 15:58:11 +0000 Subject: [PATCH] Fix shl folding in DAG combiner. Summary: The code responsible for shl folding in the DAGCombiner was assuming incorrectly that all constants are less than 64 bits. This patch simply changes the way values are compared. Test Plan: A regression test included. Reviewers: andreadb Reviewed By: andreadb Subscribers: andreadb, test, llvm-commits Differential Revision: http://reviews.llvm.org/D10602 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240291 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- test/CodeGen/X86/fold-vector-shl-crash.ll | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/X86/fold-vector-shl-crash.ll diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index bc2e5f13d43..80a1b5b3be7 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4275,7 +4275,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) { if (isNullConstant(N0)) return N0; // fold (shl x, c >= size(x)) -> undef - if (N1C && N1C->getZExtValue() >= OpSizeInBits) + if (N1C && N1C->getAPIntValue().uge(OpSizeInBits)) return DAG.getUNDEF(VT); // fold (shl x, 0) -> x if (N1C && N1C->isNullValue()) diff --git a/test/CodeGen/X86/fold-vector-shl-crash.ll b/test/CodeGen/X86/fold-vector-shl-crash.ll new file mode 100644 index 00000000000..b0341e0739c --- /dev/null +++ b/test/CodeGen/X86/fold-vector-shl-crash.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s | FileCheck %s + +;CHECK-LABEL: test +define <2 x i256> @test() { + %S = shufflevector <2 x i256> zeroinitializer, <2 x i256> , <2 x i32> + %B = shl <2 x i256> %S, ; DAG Combiner crashes here + ret <2 x i256> %B +} -- 2.11.0