From 39dfb0ff848be6b380ca81ff95d4ca4e0ae09c76 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 7 Jul 2011 03:55:05 +0000 Subject: [PATCH] Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARM.td | 140 ++++++++++++------------ lib/Target/ARM/ARMSubtarget.cpp | 17 ++- lib/Target/ARM/ARMSubtarget.h | 47 ++++---- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 33 +++--- test/CodeGen/ARM/2009-10-30.ll | 2 +- test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll | 2 +- test/CodeGen/ARM/armv4.ll | 8 +- test/CodeGen/ARM/bfx.ll | 2 +- test/CodeGen/ARM/call.ll | 4 +- test/CodeGen/ARM/globals.ll | 8 +- test/CodeGen/ARM/hello.ll | 6 +- test/CodeGen/ARM/iabs.ll | 2 +- test/CodeGen/ARM/ifcvt1.ll | 4 +- test/CodeGen/ARM/ifcvt2.ll | 2 +- test/CodeGen/ARM/ifcvt3.ll | 6 +- test/CodeGen/ARM/indirectbr.ll | 4 +- test/CodeGen/ARM/ldr_frame.ll | 2 +- test/CodeGen/ARM/phi.ll | 4 +- test/CodeGen/ARM/prefetch.ll | 4 +- test/CodeGen/ARM/truncstore-dag-combine.ll | 4 +- test/CodeGen/Thumb/barrier.ll | 2 +- test/CodeGen/Thumb2/thumb2-clz.ll | 2 +- test/CodeGen/Thumb2/thumb2-rev.ll | 2 +- test/MC/ARM/prefetch.ll | 4 +- 24 files changed, 161 insertions(+), 150 deletions(-) diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 6d3a42fa400..4e170f5524a 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -21,12 +21,14 @@ include "llvm/Target/Target.td" // ARM Subtarget features. // -def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2", +def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", "Enable VFP2 instructions">; -def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3", - "Enable VFP3 instructions">; -def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", - "Enable NEON instructions">; +def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", + "Enable VFP3 instructions", + [FeatureVFP2]>; +def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", + "Enable NEON instructions", + [FeatureVFP3]>; def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", "Enable Thumb2 instructions">; def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", @@ -84,33 +86,23 @@ def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", "Supports Multiprocessing extension">; // ARM architectures. -def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T", +def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", "ARM v4T">; -def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T", - "ARM v5T">; -def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE", - "ARM v5TE, v5TEj, v5TExp">; -def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6", - "ARM v6">; -def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M", - "ARM v6m", - [FeatureNoARM, FeatureDB]>; -def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2", +def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", + "ARM v5T", + [HasV4TOps]>; +def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", + "ARM v5TE, v5TEj, v5TExp", + [HasV5TOps]>; +def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", + "ARM v6", + [HasV5TEOps]>; +def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", "ARM v6t2", - [FeatureThumb2, FeatureDSPThumb2]>; -def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A", - "ARM v7A", - [FeatureThumb2, FeatureNEON, FeatureDB, - FeatureDSPThumb2]>; -def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M", - "ARM v7M", - [FeatureThumb2, FeatureNoARM, FeatureDB, - FeatureHWDiv]>; -def ArchV7EM : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM", - "ARM v7E-M", - [FeatureThumb2, FeatureNoARM, FeatureDB, - FeatureHWDiv, FeatureDSPThumb2, - FeatureT2XtPk]>; + [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>; +def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", + "ARM v7", + [HasV6T2Ops]>; //===----------------------------------------------------------------------===// // ARM Processors supported. @@ -145,64 +137,76 @@ def : ProcNoItin<"strongarm1100", []>; def : ProcNoItin<"strongarm1110", []>; // V4T Processors. -def : ProcNoItin<"arm7tdmi", [ArchV4T]>; -def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>; -def : ProcNoItin<"arm710t", [ArchV4T]>; -def : ProcNoItin<"arm720t", [ArchV4T]>; -def : ProcNoItin<"arm9", [ArchV4T]>; -def : ProcNoItin<"arm9tdmi", [ArchV4T]>; -def : ProcNoItin<"arm920", [ArchV4T]>; -def : ProcNoItin<"arm920t", [ArchV4T]>; -def : ProcNoItin<"arm922t", [ArchV4T]>; -def : ProcNoItin<"arm940t", [ArchV4T]>; -def : ProcNoItin<"ep9312", [ArchV4T]>; +def : ProcNoItin<"arm7tdmi", [HasV4TOps]>; +def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>; +def : ProcNoItin<"arm710t", [HasV4TOps]>; +def : ProcNoItin<"arm720t", [HasV4TOps]>; +def : ProcNoItin<"arm9", [HasV4TOps]>; +def : ProcNoItin<"arm9tdmi", [HasV4TOps]>; +def : ProcNoItin<"arm920", [HasV4TOps]>; +def : ProcNoItin<"arm920t", [HasV4TOps]>; +def : ProcNoItin<"arm922t", [HasV4TOps]>; +def : ProcNoItin<"arm940t", [HasV4TOps]>; +def : ProcNoItin<"ep9312", [HasV4TOps]>; // V5T Processors. -def : ProcNoItin<"arm10tdmi", [ArchV5T]>; -def : ProcNoItin<"arm1020t", [ArchV5T]>; +def : ProcNoItin<"arm10tdmi", [HasV5TOps]>; +def : ProcNoItin<"arm1020t", [HasV5TOps]>; // V5TE Processors. -def : ProcNoItin<"arm9e", [ArchV5TE]>; -def : ProcNoItin<"arm926ej-s", [ArchV5TE]>; -def : ProcNoItin<"arm946e-s", [ArchV5TE]>; -def : ProcNoItin<"arm966e-s", [ArchV5TE]>; -def : ProcNoItin<"arm968e-s", [ArchV5TE]>; -def : ProcNoItin<"arm10e", [ArchV5TE]>; -def : ProcNoItin<"arm1020e", [ArchV5TE]>; -def : ProcNoItin<"arm1022e", [ArchV5TE]>; -def : ProcNoItin<"xscale", [ArchV5TE]>; -def : ProcNoItin<"iwmmxt", [ArchV5TE]>; +def : ProcNoItin<"arm9e", [HasV5TEOps]>; +def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>; +def : ProcNoItin<"arm946e-s", [HasV5TEOps]>; +def : ProcNoItin<"arm966e-s", [HasV5TEOps]>; +def : ProcNoItin<"arm968e-s", [HasV5TEOps]>; +def : ProcNoItin<"arm10e", [HasV5TEOps]>; +def : ProcNoItin<"arm1020e", [HasV5TEOps]>; +def : ProcNoItin<"arm1022e", [HasV5TEOps]>; +def : ProcNoItin<"xscale", [HasV5TEOps]>; +def : ProcNoItin<"iwmmxt", [HasV5TEOps]>; // V6 Processors. -def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>; -def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2, +def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>; +def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, FeatureHasSlowFPVMLx]>; -def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>; -def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2, +def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>; +def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, FeatureHasSlowFPVMLx]>; -def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>; -def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2, +def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>; +def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, FeatureHasSlowFPVMLx]>; // V6M Processors. -def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>; +def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM, + FeatureDB]>; // V6T2 Processors. -def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>; -def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2, +def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops]>; +def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2, FeatureHasSlowFPVMLx]>; -// V7 Processors. +// V7a Processors. def : Processor<"cortex-a8", CortexA8Itineraries, - [ArchV7A, ProcA8]>; + [ProcA8, HasV7Ops, FeatureNEON, FeatureDB, + FeatureDSPThumb2]>; def : Processor<"cortex-a9", CortexA9Itineraries, - [ArchV7A, ProcA9]>; + [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, + FeatureDSPThumb2]>; def : Processor<"cortex-a9-mp", CortexA9Itineraries, - [ArchV7A, ProcA9, FeatureMP]>; + [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, + FeatureDSPThumb2, FeatureMP]>; // V7M Processors. -def : ProcNoItin<"cortex-m3", [ArchV7M]>; -def : ProcNoItin<"cortex-m4", [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>; +def : ProcNoItin<"cortex-m3", [HasV7Ops, + FeatureThumb2, FeatureNoARM, FeatureDB, + FeatureHWDiv]>; + +// V7EM Processors. +def : ProcNoItin<"cortex-m4", [HasV7Ops, + FeatureThumb2, FeatureNoARM, FeatureDB, + FeatureHWDiv, FeatureDSPThumb2, + FeatureT2XtPk, FeatureVFP2, + FeatureVFPOnlySP]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index da572d2e5ee..4affc157152 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -39,9 +39,16 @@ StrictAlign("arm-strict-align", cl::Hidden, ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) : ARMGenSubtargetInfo() - , ARMArchVersion(V4) , ARMProcFamily(Others) - , ARMFPUType(None) + , HasV4TOps(false) + , HasV5TOps(false) + , HasV5TEOps(false) + , HasV6Ops(false) + , HasV6T2Ops(false) + , HasV7Ops(false) + , HasVFPv2(false) + , HasVFPv3(false) + , HasNEON(false) , UseNEONForSinglePrecisionFP(false) , SlowFPVMLx(false) , HasVMLxForwarding(false) @@ -89,8 +96,8 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a // ARM version or CPU and then remove this. - if (ARMArchVersion < V6T2 && hasThumb2()) - ARMArchVersion = V6T2; + if (!HasV6T2Ops && hasThumb2()) + HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUString); @@ -104,7 +111,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, if (!isTargetDarwin()) UseMovt = hasV6T2Ops(); else { - IsR9Reserved = ReserveR9 | (ARMArchVersion < V6); + IsR9Reserved = ReserveR9 | !HasV6Ops; UseMovt = DarwinUseMOVT && hasV6T2Ops(); } diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index 6969c38016b..5fad9a777d6 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -28,27 +28,27 @@ class GlobalValue; class ARMSubtarget : public ARMGenSubtargetInfo { protected: - enum ARMArchEnum { - V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M, V7EM - }; - enum ARMProcFamilyEnum { Others, CortexA8, CortexA9 }; - enum ARMFPEnum { - None, VFPv2, VFPv3, NEON - }; - - /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, - /// V6, V6T2, V7A, V7M, V7EM. - ARMArchEnum ARMArchVersion; - /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. ARMProcFamilyEnum ARMProcFamily; - /// ARMFPUType - Floating Point Unit type. - ARMFPEnum ARMFPUType; + /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops - + /// Specify whether target support specific ARM ISA variants. + bool HasV4TOps; + bool HasV5TOps; + bool HasV5TEOps; + bool HasV6Ops; + bool HasV6T2Ops; + bool HasV7Ops; + + /// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are + /// supported. + bool HasVFPv2; + bool HasVFPv3; + bool HasNEON; /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been /// specified. Use the method useNEONForSinglePrecisionFP() to @@ -172,23 +172,24 @@ protected: void computeIssueWidth(); - bool hasV4TOps() const { return ARMArchVersion >= V4T; } - bool hasV5TOps() const { return ARMArchVersion >= V5T; } - bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } - bool hasV6Ops() const { return ARMArchVersion >= V6; } - bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } - bool hasV7Ops() const { return ARMArchVersion >= V7A; } + bool hasV4TOps() const { return HasV4TOps; } + bool hasV5TOps() const { return HasV5TOps; } + bool hasV5TEOps() const { return HasV5TEOps; } + bool hasV6Ops() const { return HasV6Ops; } + bool hasV6T2Ops() const { return HasV6T2Ops; } + bool hasV7Ops() const { return HasV7Ops; } bool isCortexA8() const { return ARMProcFamily == CortexA8; } bool isCortexA9() const { return ARMProcFamily == CortexA9; } bool hasARMOps() const { return !NoARM; } - bool hasVFP2() const { return ARMFPUType >= VFPv2; } - bool hasVFP3() const { return ARMFPUType >= VFPv3; } - bool hasNEON() const { return ARMFPUType >= NEON; } + bool hasVFP2() const { return HasVFPv2; } + bool hasVFP3() const { return HasVFPv3; } + bool hasNEON() const { return HasNEON; } bool useNEONForSinglePrecisionFP() const { return hasNEON() && UseNEONForSinglePrecisionFP; } + bool hasDivide() const { return HasHardwareDivide; } bool hasT2ExtractPack() const { return HasT2ExtractPack; } bool hasDataBarrier() const { return HasDataBarrier; } diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index f2b6d252245..2d5c219ae48 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -91,29 +91,28 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) { if (Idx) { unsigned SubVer = TT[Idx]; if (SubVer >= '7' && SubVer <= '9') { - ARMArchFeature = "+v7a"; if (Len >= Idx+2 && TT[Idx+1] == 'm') { - ARMArchFeature = "+v7m"; + // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv + ARMArchFeature = "+v7,+noarm,+db,+hwdiv"; } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { - ARMArchFeature = "+v7em"; - } + // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2, + // FeatureT2XtPk + ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk"; + } else + // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2 + ARMArchFeature = "+v7,+neon,+db,+t2dsp"; } else if (SubVer == '6') { - ARMArchFeature = "+v6"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') ARMArchFeature = "+v6t2"; - } + else + ARMArchFeature = "+v6"; } else if (SubVer == '5') { - ARMArchFeature = "+v5t"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') ARMArchFeature = "+v5te"; - } - } else if (SubVer == '4') { - if (Len >= Idx+2 && TT[Idx+1] == 't') { - ARMArchFeature = "+v4t"; - } else { - ARMArchFeature = ""; - } - } + else + ARMArchFeature = "+v5t"; + } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't') + ARMArchFeature = "+v4t"; } return ARMArchFeature; diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll index 87d1a8b9e9a..e46ab1eb2ab 100644 --- a/test/CodeGen/ARM/2009-10-30.ll +++ b/test/CodeGen/ARM/2009-10-30.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s ; This test checks that the address of the varg arguments is correctly ; computed when there are 5 or more regular arguments. diff --git a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll index ee443febcc1..99db63713d4 100644 --- a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll +++ b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll @@ -1,7 +1,7 @@ ; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \ -; RUN: -mattr=-neon -mattr=+vfp2 \ +; RUN: -mattr=-neon,-vfp3,+vfp2 \ ; RUN: -arm-reserve-r9 -filetype=obj -o - | \ ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s diff --git a/test/CodeGen/ARM/armv4.ll b/test/CodeGen/ARM/armv4.ll index ef722de01d2..6b213d564bd 100644 --- a/test/CodeGen/ARM/armv4.ll +++ b/test/CodeGen/ARM/armv4.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=arm-unknown-eabi | FileCheck %s -check-prefix=THUMB -; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB -; RUN: llc < %s -mtriple=arm-unknown-eabi -mattr=+v6 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB diff --git a/test/CodeGen/ARM/bfx.ll b/test/CodeGen/ARM/bfx.ll index fcca191a016..519c1353a38 100644 --- a/test/CodeGen/ARM/bfx.ll +++ b/test/CodeGen/ARM/bfx.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s define i32 @sbfx1(i32 %a) { ; CHECK: sbfx1 diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll index c020b6fbd24..0f9543f0a19 100644 --- a/test/CodeGen/ARM/call.ll +++ b/test/CodeGen/ARM/call.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4 +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s -check-prefix=CHECKV4 ; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi\ ; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF @t = weak global i32 ()* null ; [#uses=1] diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index ccb14280df9..5e7e3f2a92e 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC -; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC @G = external global i32 diff --git a/test/CodeGen/ARM/hello.ll b/test/CodeGen/ARM/hello.ll index bfed7a6630b..9f46ae078d8 100644 --- a/test/CodeGen/ARM/hello.ll +++ b/test/CodeGen/ARM/hello.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=arm -; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1 -; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1 +; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \ ; RUN: grep mov | count 2 -; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2 +; RUN: llc < %s -mtriple=armv6-apple-darwin | grep mov | count 2 @str = internal constant [12 x i8] c"Hello World\00" diff --git a/test/CodeGen/ARM/iabs.ll b/test/CodeGen/ARM/iabs.ll index 63808b238bf..c01c041cfe8 100644 --- a/test/CodeGen/ARM/iabs.ll +++ b/test/CodeGen/ARM/iabs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s ;; Integer absolute value, should produce something as good as: ARM: ;; add r3, r0, r0, asr #31 diff --git a/test/CodeGen/ARM/ifcvt1.ll b/test/CodeGen/ARM/ifcvt1.ll index e6aa044564a..b073a05fc9c 100644 --- a/test/CodeGen/ARM/ifcvt1.ll +++ b/test/CodeGen/ARM/ifcvt1.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep bx | count 1 +; RUN: llc < %s -march=arm -mattr=+v4t +; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 1 define i32 @t1(i32 %a, i32 %b) { %tmp2 = icmp eq i32 %a, 0 diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll index 7b9d0cf32cf..1bca10a7c64 100644 --- a/test/CodeGen/ARM/ifcvt2.ll +++ b/test/CodeGen/ARM/ifcvt2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK: t1: diff --git a/test/CodeGen/ARM/ifcvt3.ll b/test/CodeGen/ARM/ifcvt3.ll index f7ebac6f2ba..3e2c578dd06 100644 --- a/test/CodeGen/ARM/ifcvt3.ll +++ b/test/CodeGen/ARM/ifcvt3.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep cmpne | count 1 -; RUN: llc < %s -march=arm | grep bx | count 2 +; RUN: llc < %s -march=arm -mattr=+v4t +; RUN: llc < %s -march=arm -mattr=+v4t | grep cmpne | count 1 +; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { switch i32 %c, label %cond_next [ diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index f0ab9dd7ea0..25a0f936544 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -relocation-model=pic -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -relocation-model=pic -mtriple=thumb-apple-darwin | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2 @nextaddr = global i8* null ; [#uses=2] diff --git a/test/CodeGen/ARM/ldr_frame.ll b/test/CodeGen/ARM/ldr_frame.ll index a3abdb603fa..f071b8922d6 100644 --- a/test/CodeGen/ARM/ldr_frame.ll +++ b/test/CodeGen/ARM/ldr_frame.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | not grep mov +; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov define i32 @f1() { %buf = alloca [32 x i32], align 4 diff --git a/test/CodeGen/ARM/phi.ll b/test/CodeGen/ARM/phi.ll index 29e17c095a7..dc1a95b0b78 100644 --- a/test/CodeGen/ARM/phi.ll +++ b/test/CodeGen/ARM/phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm < %s | FileCheck %s +; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s ; define i32 @test1(i1 %a, i32* %b) { @@ -20,4 +20,4 @@ end: %r = load i32* %gep ; CHECK-NEXT: bx lr ret i32 %r -} \ No newline at end of file +} diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll index 250a34e8b0e..9c8ff2b4096 100644 --- a/test/CodeGen/ARM/prefetch.ll +++ b/test/CodeGen/ARM/prefetch.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld -; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 -; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP ; rdar://8601536 diff --git a/test/CodeGen/ARM/truncstore-dag-combine.ll b/test/CodeGen/ARM/truncstore-dag-combine.ll index 2da08b60e86..5665440aa1d 100644 --- a/test/CodeGen/ARM/truncstore-dag-combine.ll +++ b/test/CodeGen/ARM/truncstore-dag-combine.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm | not grep orr -; RUN: llc < %s -march=arm | not grep mov +; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr +; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov define void @bar(i8* %P, i16* %Q) { entry: diff --git a/test/CodeGen/Thumb/barrier.ll b/test/CodeGen/Thumb/barrier.ll index 419c3baa3da..d39b50f0a9d 100644 --- a/test/CodeGen/Thumb/barrier.ll +++ b/test/CodeGen/Thumb/barrier.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=V6 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6 -; RUN: llc < %s -march=thumb -mattr=+v6m | FileCheck %s -check-prefix=V6M +; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=V6M declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1) diff --git a/test/CodeGen/Thumb2/thumb2-clz.ll b/test/CodeGen/Thumb2/thumb2-clz.ll index 74728bfcc5a..00a54a0f195 100644 --- a/test/CodeGen/Thumb2/thumb2-clz.ll +++ b/test/CodeGen/Thumb2/thumb2-clz.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s define i32 @f1(i32 %a) { ; CHECK: f1: diff --git a/test/CodeGen/Thumb2/thumb2-rev.ll b/test/CodeGen/Thumb2/thumb2-rev.ll index 2cee2e3d6fc..b469bbd3f7b 100644 --- a/test/CodeGen/Thumb2/thumb2-rev.ll +++ b/test/CodeGen/Thumb2/thumb2-rev.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a,+t2xtpk | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7,+t2xtpk | FileCheck %s define i32 @f1(i32 %a) { ; CHECK: f1: diff --git a/test/MC/ARM/prefetch.ll b/test/MC/ARM/prefetch.ll index 674b8f323f0..e77fdb12124 100644 --- a/test/MC/ARM/prefetch.ll +++ b/test/MC/ARM/prefetch.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7a,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7a -show-mc-encoding | FileCheck %s -check-prefix=T2 +; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7 -show-mc-encoding | FileCheck %s -check-prefix=T2 ; rdar://8924681 define void @t1(i8* %ptr) nounwind { -- 2.11.0