From 3a98382e184738bdf8626b6216ba49ae41383572 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Fri, 14 Apr 2017 16:21:55 +0000 Subject: [PATCH] [Hexagon] Fix a latent problem with interpreting live-in lane masks A non-zero lane mask on a register with no subregister means that the whole register is live-in. It is equivalent to a full mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300335 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonBlockRanges.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/lib/Target/Hexagon/HexagonBlockRanges.cpp b/lib/Target/Hexagon/HexagonBlockRanges.cpp index 721cf041728..1640b40c164 100644 --- a/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -232,14 +232,16 @@ HexagonBlockRanges::RegisterSet HexagonBlockRanges::getLiveIns( const TargetRegisterInfo &TRI) { RegisterSet LiveIns; RegisterSet Tmp; + for (auto I : B.liveins()) { - if (I.LaneMask.all()) { - Tmp.insert({I.PhysReg,0}); + MCSubRegIndexIterator S(I.PhysReg, &TRI); + if (I.LaneMask.all() || (I.LaneMask.any() && !S.isValid())) { + Tmp.insert({I.PhysReg, 0}); continue; } - for (MCSubRegIndexIterator S(I.PhysReg, &TRI); S.isValid(); ++S) { - LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex()); - if ((M & I.LaneMask).any()) + for (; S.isValid(); ++S) { + unsigned SI = S.getSubRegIndex(); + if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any()) Tmp.insert({S.getSubReg(), 0}); } } -- 2.11.0