From 3d1d6d904346bcc3e0db5ca429556132225d435f Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 6 Jan 2015 19:03:20 +0000 Subject: [PATCH] [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225283 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonISelLowering.h | 3 +- lib/Target/Hexagon/HexagonInstrInfoV4.td | 92 ++++++++++++++++++++++++++++ lib/Target/Hexagon/HexagonOperands.td | 7 +++ test/MC/Disassembler/Hexagon/system_user.txt | 2 + test/MC/Disassembler/Hexagon/xtype_pred.txt | 6 ++ 5 files changed, 109 insertions(+), 1 deletion(-) diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 680c228e6a7..88743df8f28 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -68,7 +68,8 @@ bool isPositiveHalfWord(SDNode *N); WrapperShuffOB, WrapperShuffOH, TC_RETURN, - EH_RETURN + EH_RETURN, + DCFETCH }; } diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 85e4dd7b6a8..60b5e22632f 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -4120,3 +4120,95 @@ def : Pat<(i32 (load FoldGlobalAddrGP:$addr)), def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr), (i32 (L4_loadri_abs FoldGlobalAddrGP:$addr))>, Requires<[HasV4T]>; + +//===----------------------------------------------------------------------===// +// :raw for of boundscheck:hi:lo insns +//===----------------------------------------------------------------------===// + +// A4_boundscheck_lo: Detect if a register is within bounds. +let hasSideEffects = 0, isCodeGenOnly = 0 in +def A4_boundscheck_lo: ALU64Inst < + (outs PredRegs:$Pd), + (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Pd = boundscheck($Rss, $Rtt):raw:lo"> { + bits<2> Pd; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1101; + + let Inst{27-23} = 0b00100; + let Inst{13} = 0b1; + let Inst{7-5} = 0b100; + let Inst{1-0} = Pd; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + } + +// A4_boundscheck_hi: Detect if a register is within bounds. +let hasSideEffects = 0, isCodeGenOnly = 0 in +def A4_boundscheck_hi: ALU64Inst < + (outs PredRegs:$Pd), + (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Pd = boundscheck($Rss, $Rtt):raw:hi"> { + bits<2> Pd; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1101; + + let Inst{27-23} = 0b00100; + let Inst{13} = 0b1; + let Inst{7-5} = 0b101; + let Inst{1-0} = Pd; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + } + +let hasSideEffects = 0 in +def A4_boundscheck : MInst < + (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt), + "$Pd=boundscheck($Rs,$Rtt)">; + +// A4_tlbmatch: Detect if a VA/ASID matches a TLB entry. +let isPredicateLate = 1, hasSideEffects = 0, isCodeGenOnly = 0 in +def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd), + (ins DoubleRegs:$Rs, IntRegs:$Rt), + "$Pd = tlbmatch($Rs, $Rt)", + [], "", ALU64_tc_2early_SLOT23> { + bits<2> Pd; + bits<5> Rs; + bits<5> Rt; + + let IClass = 0b1101; + let Inst{27-23} = 0b00100; + let Inst{20-16} = Rs; + let Inst{13} = 0b1; + let Inst{12-8} = Rt; + let Inst{7-5} = 0b011; + let Inst{1-0} = Pd; + } + +// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH +// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore. +// We don't really want either one here. +def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>; +def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH, + [SDNPHasChain]>; + +// Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't +// really do a load. +let hasSideEffects = 1, mayLoad = 0, isCodeGenOnly = 0 in +def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3), + "dcfetch($Rs + #$u11_3)", + [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)], + "", LD_tc_ld_SLOT0> { + bits<5> Rs; + bits<14> u11_3; + + let IClass = 0b1001; + let Inst{27-21} = 0b0100000; + let Inst{20-16} = Rs; + let Inst{13} = 0b0; + let Inst{10-0} = u11_3{13-3}; +} diff --git a/lib/Target/Hexagon/HexagonOperands.td b/lib/Target/Hexagon/HexagonOperands.td index 9d58ce987aa..5a6de0ae274 100644 --- a/lib/Target/Hexagon/HexagonOperands.td +++ b/lib/Target/Hexagon/HexagonOperands.td @@ -259,6 +259,13 @@ def u16_s8ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<16,8>(v); }]>; +def u11_3ImmPred : PatLeaf<(i32 imm), [{ + // True if the immediate fits in a 14-bit unsigned field, and the lowest + // three bits are 0. + int64_t v = (int64_t)N->getSExtValue(); + return isShiftedUInt<11,3>(v); +}]>; + def u9ImmPred : PatLeaf<(i32 imm), [{ // u9ImmPred predicate - True if the immediate fits in a 9-bit unsigned // field. diff --git a/test/MC/Disassembler/Hexagon/system_user.txt b/test/MC/Disassembler/Hexagon/system_user.txt index f13b2b67f8e..51d082a9e18 100644 --- a/test/MC/Disassembler/Hexagon/system_user.txt +++ b/test/MC/Disassembler/Hexagon/system_user.txt @@ -6,5 +6,7 @@ # CHECK: r17:16 = memd_locked(r21) 0x00 0xc0 0x00 0xa8 # CHECK: barrier +0x15 0xc0 0x11 0x94 +# CHECK: dcfetch(r17 + #168) 0x00 0xc0 0x51 0x62 # CHECK: trace(r17) diff --git a/test/MC/Disassembler/Hexagon/xtype_pred.txt b/test/MC/Disassembler/Hexagon/xtype_pred.txt index 3336414413a..0fa4f05bce8 100644 --- a/test/MC/Disassembler/Hexagon/xtype_pred.txt +++ b/test/MC/Disassembler/Hexagon/xtype_pred.txt @@ -1,5 +1,9 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +0x83 0xf4 0x10 0xd2 +# CHECK: p3 = boundscheck(r17:16, r21:20):raw:lo +0xa3 0xf4 0x10 0xd2 +# CHECK: p3 = boundscheck(r17:16, r21:20):raw:hi 0x43 0xd5 0xd1 0xc7 # CHECK: p3 = cmpb.gt(r17, r21) 0xc3 0xd5 0xd1 0xc7 @@ -44,6 +48,8 @@ # CHECK: p3 = !bitsclr(r17, r21) 0x10 0xc3 0x00 0x86 # CHECK: r17:16 = mask(p3) +0x63 0xf5 0x10 0xd2 +# CHECK: p3 = tlbmatch(r17:16, r21) 0x03 0xc0 0x45 0x85 # CHECK: p3 = r5 0x05 0xc0 0x43 0x89 -- 2.11.0