From 3d35fe712e3a775548aeb6b6bdc75b7f1766583c Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jouni=20H=C3=B6gander?= Date: Tue, 24 Jan 2023 12:26:35 +0200 Subject: [PATCH] drm/i915/psr: Implement Wa_14014971492 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Implement Wa_14014971492 and apply it for affected platforms. Bspec: 52890, 54369, 55378, 66624 v2: Adjust platforms where applied Cc: Rodrigo Vivi Cc: Mika Kahola Cc: José Roberto de Souza Signed-off-by: Jouni Högander Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20230124102636.2567292-2-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7d4a15a283a0..7a72e15e6836 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1842,6 +1842,12 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, if (full_update) goto skip_sel_fetch_set_loop; + /* Wa_14014971492 */ + if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || + IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) && + crtc_state->splitter.enable) + pipe_clip.y1 = 0; + ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); if (ret) return ret; -- 2.11.0