From 3d8bdc301352ff100f366daed0614a4ce765f64e Mon Sep 17 00:00:00 2001 From: aoliva Date: Mon, 28 Jun 2004 19:26:37 +0000 Subject: [PATCH] sim/h8300/ChangeLog: 2003-07-23 Richard Sandiford * compile.c (sim_resume): Make sure that dst.reg refers to the right register byte in mova/sz.l @(dd,RnL),ERn. 2003-07-21 Richard Sandiford * compile.c (sim_resume): Zero-extend immediate to muls, mulsu, mulxs, divs and divxs. sim/testsuite/sim/h8300/ChangeLog: 2003-07-22 Michael Snyder * mul.s: Don't try to use negative immediate (it's always unsigned). * div.s: Ditto. --- sim/h8300/ChangeLog | 7 +++++ sim/h8300/compile.c | 64 ++++++--------------------------------- sim/testsuite/sim/h8300/ChangeLog | 7 +++++ sim/testsuite/sim/h8300/div.s | 12 ++++---- sim/testsuite/sim/h8300/mul.s | 16 +++++----- 5 files changed, 37 insertions(+), 69 deletions(-) diff --git a/sim/h8300/ChangeLog b/sim/h8300/ChangeLog index b77fcfc529..d1a4fa09c8 100644 --- a/sim/h8300/ChangeLog +++ b/sim/h8300/ChangeLog @@ -1,5 +1,12 @@ 2004-06-28 Alexandre Oliva + 2003-07-23 Richard Sandiford + * compile.c (sim_resume): Make sure that dst.reg refers to the + right register byte in mova/sz.l @(dd,RnL),ERn. + 2003-07-21 Richard Sandiford + * compile.c (sim_resume): Zero-extend immediate to muls, mulsu, + mulxs, divs and divxs. + * compile.c (sim_load): Update sd->memory_size. 2004-06-10 Michael Snyder diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c index 3e8992c09c..3c11e8263d 100644 --- a/sim/h8300/compile.c +++ b/sim/h8300/compile.c @@ -2037,7 +2037,10 @@ sim_resume (SIM_DESC sd, int step, int siggnal) code->op3.literal = 0; if (OP_KIND (code->src.type) == OP_INDEXB) - code->dst.type = X (OP_REG, SB); + { + code->dst.type = X (OP_REG, SB); + code->dst.reg = code->op3.reg + 8; + } else code->dst.type = X (OP_REG, SW); } @@ -3886,13 +3889,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfff0; - else - ea = SEXTSHORT (ea); - + ea = SEXTSHORT (ea); res = SEXTSHORT (ea * SEXTSHORT (rd)); n = res & 0x8000; @@ -3907,11 +3904,6 @@ sim_resume (SIM_DESC sd, int step, int siggnal) fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - res = ea * rd; n = res & 0x80000000; @@ -3925,11 +3917,6 @@ sim_resume (SIM_DESC sd, int step, int siggnal) fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - /* Compute upper 32 bits of the 64-bit result. */ res = (((long long) ea) * ((long long) rd)) >> 32; @@ -3985,13 +3972,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - else - ea = SEXTCHAR (ea); - + ea = SEXTCHAR (ea); res = ea * SEXTCHAR (rd); n = res & 0x8000; @@ -4006,13 +3987,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfff0; - else - ea = SEXTSHORT (ea); - + ea = SEXTSHORT (ea); res = ea * SEXTSHORT (rd & 0xffff); n = res & 0x80000000; @@ -4103,11 +4078,6 @@ sim_resume (SIM_DESC sd, int step, int siggnal) fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - if (ea) { res = SEXTSHORT (rd) / SEXTSHORT (ea); @@ -4129,11 +4099,6 @@ sim_resume (SIM_DESC sd, int step, int siggnal) fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - if (ea) { res = rd / ea; @@ -4205,13 +4170,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) goto end; rd = SEXTSHORT (rd); - - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - else - ea = SEXTCHAR (ea); + ea = SEXTCHAR (ea); if (ea) { @@ -4236,12 +4195,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - else - ea = SEXTSHORT (ea); + ea = SEXTSHORT (ea); if (ea) { diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog index a90793a9ee..21c0266382 100644 --- a/sim/testsuite/sim/h8300/ChangeLog +++ b/sim/testsuite/sim/h8300/ChangeLog @@ -1,3 +1,10 @@ +2004-06-28 Alexandre Oliva + + 2003-07-22 Michael Snyder + * mul.s: Don't try to use negative immediate (it's always + unsigned). + * div.s: Ditto. + 2004-06-24 Alexandre Oliva 2004-06-17 Alexandre Oliva diff --git a/sim/testsuite/sim/h8300/div.s b/sim/testsuite/sim/h8300/div.s index 518b62f952..fd53bafa62 100644 --- a/sim/testsuite/sim/h8300/div.s +++ b/sim/testsuite/sim/h8300/div.s @@ -41,9 +41,9 @@ divs_w_imm4_reg: set_grs_a5a5 ;; divs.w xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - divs.w #-2:4, r1 + divs.w #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -88,9 +88,9 @@ divs_l_imm4_reg: set_grs_a5a5 ;; divs.l xx:4, rd - mov.l #320000, er1 + mov.l #-320000, er1 set_ccr_zero - divs.l #-2:4, er1 + divs.l #2:4, er1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -221,9 +221,9 @@ divxs_b_imm4_reg: set_grs_a5a5 ;; divxs.b xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - divxs.b #-2:4, r1 + divxs.b #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set diff --git a/sim/testsuite/sim/h8300/mul.s b/sim/testsuite/sim/h8300/mul.s index 70ab7ec120..02b9e9f846 100644 --- a/sim/testsuite/sim/h8300/mul.s +++ b/sim/testsuite/sim/h8300/mul.s @@ -41,9 +41,9 @@ muls_w_imm4_reg: set_grs_a5a5 ;; muls.w xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - muls.w #-2:4, r1 + muls.w #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -88,9 +88,9 @@ muls_l_imm4_reg: set_grs_a5a5 ;; muls.l xx:4, rd - mov.l #320000, er1 + mov.l #-320000, er1 set_ccr_zero - muls.l #-2:4, er1 + muls.l #2:4, er1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -308,9 +308,9 @@ mulxs_b_imm4_reg: set_grs_a5a5 ;; mulxs.b xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - mulxs.b #-2:4, r1 + mulxs.b #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -408,9 +408,9 @@ mulxu_b_imm4_reg: set_grs_a5a5 ;; mulxu.b xx:4, rd - mov.b #32, r1l + mov.b #-32, r1l set_ccr_zero - mulxu.b #-2:4, r1 + mulxu.b #2:4, r1 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 test_cc_clear -- 2.11.0