From 3f451ea18e210d91b211d48abe062a9a43cf360b Mon Sep 17 00:00:00 2001 From: Hiroshi Inoue Date: Tue, 9 Apr 2019 08:40:02 +0000 Subject: [PATCH] [PowerPC] fix trivial typos in comment, NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357981 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCFrameLowering.cpp | 2 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 6 +++--- lib/Target/PowerPC/PPCISelLowering.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp index efe06de21e6..9ff8312d988 100644 --- a/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -756,7 +756,7 @@ bool PPCFrameLowering::stackUpdateCanBeMoved(MachineFunction &MF) const { if (FI->hasFastCall() || FI->usesPICBase()) return false; - // Finally we can move the stack update if we do not require regiser + // Finally we can move the stack update if we do not require register // scavenging. Register scavenging can introduce more spills and so // may make the frame size larger than we have computed. return !RegInfo->requiresFrameIndexScavenging(MF); diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index d544d50690c..610e7c0de10 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -2372,7 +2372,7 @@ public: // Here we try to match complex bit permutations into a set of // rotate-and-shift/shift/and/or instructions, using a set of heuristics - // known to produce optimial code for common cases (like i32 byte swapping). + // known to produce optimal code for common cases (like i32 byte swapping). SDNode *Select(SDNode *N) { Memoizer.clear(); auto Result = @@ -4213,12 +4213,12 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG, // Without this setb optimization, the outer SELECT_CC will be manually // selected to SELECT_CC_I4/SELECT_CC_I8 Pseudo, then expand-isel-pseudos pass - // transforms pseduo instruction to isel instruction. When there are more than + // transforms pseudo instruction to isel instruction. When there are more than // one use for result like zext/sext, with current optimization we only see // isel is replaced by setb but can't see any significant gain. Since // setb has longer latency than original isel, we should avoid this. Another // point is that setb requires comparison always kept, it can break the - // oppotunity to get the comparison away if we have in future. + // opportunity to get the comparison away if we have in future. if (!SetOrSelCC.hasOneUse() || (!InnerIsSel && !FalseRes.hasOneUse())) return false; diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 93920e9f9a9..ef531115466 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -40,7 +40,7 @@ namespace llvm { // the enum. The order of elements in this enum matters! // Values that are added after this entry: // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE - // are considerd memory opcodes and are treated differently than entries + // are considered memory opcodes and are treated differently than entries // that come before it. For example, ADD or MUL should be placed before // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come // after it. @@ -192,7 +192,7 @@ namespace llvm { /// Direct move from a GPR to a VSX register (zero) MTVSRZ, - /// Direct move of 2 consective GPR to a VSX register. + /// Direct move of 2 consecutive GPR to a VSX register. BUILD_FP128, /// Extract a subvector from signed integer vector and convert to FP. -- 2.11.0