From 419fa631cdc4558acabc006ad6c006d236971508 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 27 Jun 2019 09:49:07 +0000 Subject: [PATCH] [GlobalISel] Remove [un]packRegs from IRTranslator Remove the last use of packRegs from IRTranslator and delete pack/unpackRegs. This introduces a fallback to DAGISel for intrinsics with aggregate arguments, since we don't have a testcase for them so it's hard to tell how we'd want to handle them. Discussed in https://reviews.llvm.org/D63551 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364514 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/GlobalISel/IRTranslator.h | 8 ------- lib/CodeGen/GlobalISel/IRTranslator.cpp | 33 ++++---------------------- 2 files changed, 4 insertions(+), 37 deletions(-) diff --git a/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/include/llvm/CodeGen/GlobalISel/IRTranslator.h index a3ca33e7645..076abcf183e 100644 --- a/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -237,14 +237,6 @@ private: bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder); - // FIXME: temporary function to expose previous interface to call lowering - // until it is refactored. - /// Combines all component registers of \p V into a single scalar with size - /// "max(Offsets) + last size". - Register packRegs(const Value &V, MachineIRBuilder &MIRBuilder); - - void unpackRegs(const Value &V, Register Src, MachineIRBuilder &MIRBuilder); - /// Returns true if the value should be split into multiple LLTs. /// If \p Offsets is given then the split type's offsets will be stored in it. /// If \p Offsets is not empty it will be cleared first. diff --git a/lib/CodeGen/GlobalISel/IRTranslator.cpp b/lib/CodeGen/GlobalISel/IRTranslator.cpp index 48b3a52f084..0827db38934 100644 --- a/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1537,34 +1537,6 @@ bool IRTranslator::translateInlineAsm(const CallInst &CI, return true; } -Register IRTranslator::packRegs(const Value &V, - MachineIRBuilder &MIRBuilder) { - ArrayRef Regs = getOrCreateVRegs(V); - ArrayRef Offsets = *VMap.getOffsets(V); - LLT BigTy = getLLTForType(*V.getType(), *DL); - - if (Regs.size() == 1) - return Regs[0]; - - Register Dst = MRI->createGenericVirtualRegister(BigTy); - MIRBuilder.buildUndef(Dst); - for (unsigned i = 0; i < Regs.size(); ++i) { - Register NewDst = MRI->createGenericVirtualRegister(BigTy); - MIRBuilder.buildInsert(NewDst, Dst, Regs[i], Offsets[i]); - Dst = NewDst; - } - return Dst; -} - -void IRTranslator::unpackRegs(const Value &V, Register Src, - MachineIRBuilder &MIRBuilder) { - ArrayRef Regs = getOrCreateVRegs(V); - ArrayRef Offsets = *VMap.getOffsets(V); - - for (unsigned i = 0; i < Regs.size(); ++i) - MIRBuilder.buildExtract(Regs[i], Src, Offsets[i]); -} - bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) { const CallInst &CI = cast(U); auto TII = MF->getTarget().getIntrinsicInfo(); @@ -1631,7 +1603,10 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) { // Some intrinsics take metadata parameters. Reject them. if (isa(Arg)) return false; - MIB.addUse(packRegs(*Arg, MIRBuilder)); + ArrayRef VRegs = getOrCreateVRegs(*Arg); + if (VRegs.size() > 1) + return false; + MIB.addUse(VRegs[0]); } // Add a MachineMemOperand if it is a target mem intrinsic. -- 2.11.0