From 4265f1d23cc9d10b9544bafc7a285ca5f143faea Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Wed, 27 May 2020 10:36:25 +0100 Subject: [PATCH] [CodeGen] Fix warnings in getZeroExtendInReg We should be using getVectorElementCount() to assert that two types have the same numbers of elements. I encountered the warnings while compiling this test: CodeGen/AArch64/sve-intrinsics-ld1.ll Differential Revision: https://reviews.llvm.org/D80616 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 2f277eee849..bd1a5a4a876 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1175,7 +1175,7 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { "getZeroExtendInReg type should be vector iff the operand " "type is vector!"); assert((!VT.isVector() || - VT.getVectorNumElements() == OpVT.getVectorNumElements()) && + VT.getVectorElementCount() == OpVT.getVectorElementCount()) && "Vector element counts must match in getZeroExtendInReg"); assert(VT.bitsLE(OpVT) && "Not extending!"); if (OpVT == VT) -- 2.11.0