From 4387b10434fe9acde582b886d16a72ec1843c0e9 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 10 Jun 2020 14:32:58 +0800 Subject: [PATCH] drm/amd/powerplay: add more members for dpm table These members can help to cache the clock frequencies for all dpm levels. Then simplifying the code for dpm level switching is possible. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h index 05c8b44e0632..c6832be8356f 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h @@ -48,6 +48,7 @@ #define SMU11_TOOL_SIZE 0x19000 +#define MAX_DPM_LEVELS 16 #define MAX_PCIE_CONF 2 #define CLK_MAP(clk, index) \ @@ -91,9 +92,17 @@ struct smu_11_0_max_sustainable_clocks { uint32_t soc_clock; }; +struct smu_11_0_dpm_clk_level { + bool enabled; + uint32_t value; +}; + struct smu_11_0_dpm_table { - uint32_t min; /* MHz */ - uint32_t max; /* MHz */ + uint32_t min; /* MHz */ + uint32_t max; /* MHz */ + uint32_t count; + bool is_fine_grained; + struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; }; struct smu_11_0_pcie_table { @@ -107,7 +116,9 @@ struct smu_11_0_dpm_tables { struct smu_11_0_dpm_table uclk_table; struct smu_11_0_dpm_table eclk_table; struct smu_11_0_dpm_table vclk_table; + struct smu_11_0_dpm_table vclk1_table; struct smu_11_0_dpm_table dclk_table; + struct smu_11_0_dpm_table dclk1_table; struct smu_11_0_dpm_table dcef_table; struct smu_11_0_dpm_table pixel_table; struct smu_11_0_dpm_table display_table; -- 2.11.0