From 43aa7bdb28c504a30f0119928b0975bd29c2729f Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Tue, 28 May 2019 18:31:36 +0000 Subject: [PATCH] [NFC][MIPS] Autogenerater madd-msub.ll test Being affected by upcoming patch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361860 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/madd-msub.ll | 651 +++++++++++++++++++++++++++-------------- 1 file changed, 435 insertions(+), 216 deletions(-) diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll index c5f7af1de20..8a1010e45f6 100644 --- a/test/CodeGen/Mips/madd-msub.ll +++ b/test/CodeGen/Mips/madd-msub.ll @@ -1,57 +1,76 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s \ -; RUN: | FileCheck %s -check-prefixes=ALL,32 -; RUN: llc -march=mips -mcpu=mips32r2 < %s \ -; RUN: | FileCheck %s -check-prefixes=ALL,32 -; RUN: llc -march=mips -mcpu=mips32r6 < %s \ -; RUN: | FileCheck %s -check-prefixes=ALL,32R6 -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s \ -; RUN: | FileCheck %s -check-prefix=DSP -; RUN: llc -march=mips -mcpu=mips64 -target-abi n64 < %s \ -; RUN: | FileCheck %s -check-prefixes=ALL,64 -; RUN: llc -march=mips -mcpu=mips64r2 -target-abi n64 < %s \ -; RUN: | FileCheck %s -check-prefixes=ALL,64 -; RUN: llc -march=mips -mcpu=mips64r6 -target-abi n64 < %s \ -; RUN: | FileCheck %s -check-prefixes=ALL,64R6 - -; FIXME: The MIPS16 test should check its output -; RUN: llc -march=mips -mattr=mips16 < %s - -; ALL-LABEL: madd1: - -; 32-DAG: sra $[[T0:[0-9]+]], $6, 31 -; 32-DAG: mtlo $6 -; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}} -; 32-DAG: [[m]]fhi $2 -; 32-DAG: [[m]]flo $3 - -; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31 -; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] -; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}} -; DSP-DAG: mfhi $2, $[[AC]] -; DSP-DAG: mflo $3, $[[AC]] - -; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6 -; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] -; 32R6-DAG: muh $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: sra $[[T4:[0-9]+]], $6, 31 -; 32R6-DAG: addu $[[T5:[0-9]+]], $[[T3]], $[[T4]] -; 32R6-DAG: addu $2, $[[T5]], $[[T2]] - -; 64-DAG: sll $[[T0:[0-9]+]], $4, 0 -; 64-DAG: sll $[[T1:[0-9]+]], $5, 0 -; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]] -; 64-DAG: [[m]]flo $[[T2:[0-9]+]] -; 64-DAG: sll $[[T3:[0-9]+]], $6, 0 -; 64-DAG: daddu $2, $[[T2]], $[[T3]] - -; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0 -; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0 -; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]] -; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0 -; 64R6-DAG: daddu $2, $[[T2]], $[[T3]] +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32 +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32 +; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,32R6 +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP +; RUN: llc -march=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64 +; RUN: llc -march=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64 +; RUN: llc -march=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64R6 +; RUN: llc -march=mips -mattr=mips16 < %s | FileCheck %s -check-prefixes=ALL,16 define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone { +; 32-LABEL: madd1: +; 32: # %bb.0: # %entry +; 32-NEXT: sra $1, $6, 31 +; 32-NEXT: mtlo $6 +; 32-NEXT: mthi $1 +; 32-NEXT: madd $5, $4 +; 32-NEXT: mfhi $2 +; 32-NEXT: jr $ra +; 32-NEXT: mflo $3 +; +; 32R6-LABEL: madd1: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: mul $1, $5, $4 +; 32R6-NEXT: addu $3, $1, $6 +; 32R6-NEXT: sltu $1, $3, $1 +; 32R6-NEXT: muh $2, $5, $4 +; 32R6-NEXT: sra $4, $6, 31 +; 32R6-NEXT: addu $2, $2, $4 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: addu $2, $2, $1 +; +; DSP-LABEL: madd1: +; DSP: # %bb.0: # %entry +; DSP-NEXT: sra $1, $6, 31 +; DSP-NEXT: mtlo $6, $ac0 +; DSP-NEXT: mthi $1, $ac0 +; DSP-NEXT: madd $ac0, $5, $4 +; DSP-NEXT: mfhi $2, $ac0 +; DSP-NEXT: jr $ra +; DSP-NEXT: mflo $3, $ac0 +; +; 64-LABEL: madd1: +; 64: # %bb.0: # %entry +; 64-NEXT: sll $1, $4, 0 +; 64-NEXT: sll $2, $5, 0 +; 64-NEXT: dmult $2, $1 +; 64-NEXT: mflo $1 +; 64-NEXT: sll $2, $6, 0 +; 64-NEXT: jr $ra +; 64-NEXT: daddu $2, $1, $2 +; +; 64R6-LABEL: madd1: +; 64R6: # %bb.0: # %entry +; 64R6-NEXT: sll $1, $4, 0 +; 64R6-NEXT: sll $2, $5, 0 +; 64R6-NEXT: dmul $1, $2, $1 +; 64R6-NEXT: sll $2, $6, 0 +; 64R6-NEXT: jr $ra +; 64R6-NEXT: daddu $2, $1, $2 +; +; 16-LABEL: madd1: +; 16: # %bb.0: # %entry +; 16-NEXT: mult $5, $4 +; 16-NEXT: mflo $2 +; 16-NEXT: mfhi $3 +; 16-NEXT: sra $4, $6, 31 +; 16-NEXT: addu $4, $3, $4 +; 16-NEXT: addu $3, $2, $6 +; 16-NEXT: sltu $3, $2 +; 16-NEXT: move $2, $24 +; 16-NEXT: addu $2, $4, $2 +; 16-NEXT: jrc $ra entry: %conv = sext i32 %a to i64 %conv2 = sext i32 %b to i64 @@ -61,36 +80,59 @@ entry: ret i64 %add } -; ALL-LABEL: madd2: - -; FIXME: We don't really need this instruction -; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0 -; 32-DAG: mtlo $6 -; 32-DAG: [[m:m]]addu ${{[45]}}, ${{[45]}} -; 32-DAG: [[m]]fhi $2 -; 32-DAG: [[m]]flo $3 - -; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0 -; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] -; DSP-DAG: maddu $[[AC]], ${{[45]}}, ${{[45]}} -; DSP-DAG: mfhi $2, $[[AC]] -; DSP-DAG: mflo $3, $[[AC]] - -; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6 -; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] -; FIXME: There's a redundant move here. We should remove it -; 32R6-DAG: muhu $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: addu $2, $[[T3]], $[[T2]] - -; 64-DAG: d[[m:m]]ult $5, $4 -; 64-DAG: [[m]]flo $[[T0:[0-9]+]] -; 64-DAG: daddu $2, $[[T0]], $6 - -; 64R6-DAG: dmul $[[T0:[0-9]+]], $5, $4 -; 64R6-DAG: daddu $2, $[[T0]], $6 - define i64 @madd2(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c) nounwind readnone { +; 32-LABEL: madd2: +; 32: # %bb.0: # %entry +; 32-NEXT: addiu $1, $zero, 0 +; 32-NEXT: mtlo $6 +; 32-NEXT: mthi $1 +; 32-NEXT: maddu $5, $4 +; 32-NEXT: mfhi $2 +; 32-NEXT: jr $ra +; 32-NEXT: mflo $3 +; +; 32R6-LABEL: madd2: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: mul $1, $5, $4 +; 32R6-NEXT: addu $3, $1, $6 +; 32R6-NEXT: sltu $1, $3, $1 +; 32R6-NEXT: muhu $2, $5, $4 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: addu $2, $2, $1 +; +; DSP-LABEL: madd2: +; DSP: # %bb.0: # %entry +; DSP-NEXT: addiu $1, $zero, 0 +; DSP-NEXT: mtlo $6, $ac0 +; DSP-NEXT: mthi $1, $ac0 +; DSP-NEXT: maddu $ac0, $5, $4 +; DSP-NEXT: mfhi $2, $ac0 +; DSP-NEXT: jr $ra +; DSP-NEXT: mflo $3, $ac0 +; +; 64-LABEL: madd2: +; 64: # %bb.0: # %entry +; 64-NEXT: dmult $5, $4 +; 64-NEXT: mflo $1 +; 64-NEXT: jr $ra +; 64-NEXT: daddu $2, $1, $6 +; +; 64R6-LABEL: madd2: +; 64R6: # %bb.0: # %entry +; 64R6-NEXT: dmul $1, $5, $4 +; 64R6-NEXT: jr $ra +; 64R6-NEXT: daddu $2, $1, $6 +; +; 16-LABEL: madd2: +; 16: # %bb.0: # %entry +; 16-NEXT: multu $5, $4 +; 16-NEXT: mflo $2 +; 16-NEXT: mfhi $4 +; 16-NEXT: addu $3, $2, $6 +; 16-NEXT: sltu $3, $2 +; 16-NEXT: move $2, $24 +; 16-NEXT: addu $2, $4, $2 +; 16-NEXT: jrc $ra entry: %conv = zext i32 %a to i64 %conv2 = zext i32 %b to i64 @@ -100,39 +142,63 @@ entry: ret i64 %add } -; ALL-LABEL: madd3: - -; 32-DAG: mthi $6 -; 32-DAG: mtlo $7 -; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}} -; 32-DAG: [[m]]fhi $2 -; 32-DAG: [[m]]flo $3 - -; DSP-DAG: mthi $6, $[[AC:ac[0-3]+]] -; DSP-DAG: mtlo $7, $[[AC]] -; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}} -; DSP-DAG: mfhi $2, $[[AC]] -; DSP-DAG: mflo $3, $[[AC]] - -; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $7 -; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $1 -; 32R6-DAG: muh $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T3]], $6 -; 32R6-DAG: addu $2, $[[T4]], $[[T2]] - -; 64-DAG: sll $[[T0:[0-9]+]], $4, 0 -; 64-DAG: sll $[[T1:[0-9]+]], $5, 0 -; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]] -; 64-DAG: [[m]]flo $[[T2:[0-9]+]] -; 64-DAG: daddu $2, $[[T2]], $6 - -; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0 -; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0 -; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]] -; 64R6-DAG: daddu $2, $[[T2]], $6 - define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone { +; 32-LABEL: madd3: +; 32: # %bb.0: # %entry +; 32-NEXT: mtlo $7 +; 32-NEXT: mthi $6 +; 32-NEXT: madd $5, $4 +; 32-NEXT: mfhi $2 +; 32-NEXT: jr $ra +; 32-NEXT: mflo $3 +; +; 32R6-LABEL: madd3: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: mul $1, $5, $4 +; 32R6-NEXT: addu $3, $1, $7 +; 32R6-NEXT: sltu $1, $3, $1 +; 32R6-NEXT: muh $2, $5, $4 +; 32R6-NEXT: addu $2, $2, $6 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: addu $2, $2, $1 +; +; DSP-LABEL: madd3: +; DSP: # %bb.0: # %entry +; DSP-NEXT: mtlo $7, $ac0 +; DSP-NEXT: mthi $6, $ac0 +; DSP-NEXT: madd $ac0, $5, $4 +; DSP-NEXT: mfhi $2, $ac0 +; DSP-NEXT: jr $ra +; DSP-NEXT: mflo $3, $ac0 +; +; 64-LABEL: madd3: +; 64: # %bb.0: # %entry +; 64-NEXT: sll $1, $4, 0 +; 64-NEXT: sll $2, $5, 0 +; 64-NEXT: dmult $2, $1 +; 64-NEXT: mflo $1 +; 64-NEXT: jr $ra +; 64-NEXT: daddu $2, $1, $6 +; +; 64R6-LABEL: madd3: +; 64R6: # %bb.0: # %entry +; 64R6-NEXT: sll $1, $4, 0 +; 64R6-NEXT: sll $2, $5, 0 +; 64R6-NEXT: dmul $1, $2, $1 +; 64R6-NEXT: jr $ra +; 64R6-NEXT: daddu $2, $1, $6 +; +; 16-LABEL: madd3: +; 16: # %bb.0: # %entry +; 16-NEXT: mult $5, $4 +; 16-NEXT: mflo $2 +; 16-NEXT: mfhi $3 +; 16-NEXT: addu $4, $3, $6 +; 16-NEXT: addu $3, $2, $7 +; 16-NEXT: sltu $3, $2 +; 16-NEXT: move $2, $24 +; 16-NEXT: addu $2, $4, $2 +; 16-NEXT: jrc $ra entry: %conv = sext i32 %a to i64 %conv2 = sext i32 %b to i64 @@ -141,10 +207,49 @@ entry: ret i64 %add } -; ALL-LABEL: madd4 -; ALL-NOT: madd ${{[0-9]+}}, ${{[0-9]+}} - define i32 @madd4(i32 %a, i32 %b, i32 %c) { +; 32-LABEL: madd4: +; 32: # %bb.0: # %entry +; 32-NEXT: mul $1, $4, $5 +; 32-NEXT: jr $ra +; 32-NEXT: addu $2, $6, $1 +; +; 32R6-LABEL: madd4: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: mul $1, $4, $5 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: addu $2, $6, $1 +; +; DSP-LABEL: madd4: +; DSP: # %bb.0: # %entry +; DSP-NEXT: mul $1, $4, $5 +; DSP-NEXT: jr $ra +; DSP-NEXT: addu $2, $6, $1 +; +; 64-LABEL: madd4: +; 64: # %bb.0: # %entry +; 64-NEXT: sll $1, $5, 0 +; 64-NEXT: sll $2, $4, 0 +; 64-NEXT: mul $1, $2, $1 +; 64-NEXT: sll $2, $6, 0 +; 64-NEXT: jr $ra +; 64-NEXT: addu $2, $2, $1 +; +; 64R6-LABEL: madd4: +; 64R6: # %bb.0: # %entry +; 64R6-NEXT: sll $1, $5, 0 +; 64R6-NEXT: sll $2, $4, 0 +; 64R6-NEXT: mul $1, $2, $1 +; 64R6-NEXT: sll $2, $6, 0 +; 64R6-NEXT: jr $ra +; 64R6-NEXT: addu $2, $2, $1 +; +; 16-LABEL: madd4: +; 16: # %bb.0: # %entry +; 16-NEXT: mult $4, $5 +; 16-NEXT: mflo $2 +; 16-NEXT: addu $2, $6, $2 +; 16-NEXT: jrc $ra entry: %mul = mul nsw i32 %a, %b %add = add nsw i32 %c, %mul @@ -152,42 +257,69 @@ entry: ret i32 %add } -; ALL-LABEL: msub1: - -; 32-DAG: sra $[[T0:[0-9]+]], $6, 31 -; 32-DAG: mtlo $6 -; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}} -; 32-DAG: [[m]]fhi $2 -; 32-DAG: [[m]]flo $3 - -; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31 -; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] -; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}} -; DSP-DAG: mfhi $2, $[[AC]] -; DSP-DAG: mflo $3, $[[AC]] - -; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: sltu $[[T1:[0-9]+]], $6, $[[T0]] -; 32R6-DAG: muh $[[T2:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: sra $[[T3:[0-9]+]], $6, 31 -; 32R6-DAG: subu $[[T4:[0-9]+]], $[[T3]], $[[T2]] -; 32R6-DAG: subu $2, $[[T4]], $[[T1]] -; 32R6-DAG: subu $3, $6, $[[T0]] - -; 64-DAG: sll $[[T0:[0-9]+]], $4, 0 -; 64-DAG: sll $[[T1:[0-9]+]], $5, 0 -; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]] -; 64-DAG: [[m]]flo $[[T2:[0-9]+]] -; 64-DAG: sll $[[T3:[0-9]+]], $6, 0 -; 64-DAG: dsubu $2, $[[T3]], $[[T2]] - -; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0 -; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0 -; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]] -; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0 -; 64R6-DAG: dsubu $2, $[[T3]], $[[T2]] - define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone { +; 32-LABEL: msub1: +; 32: # %bb.0: # %entry +; 32-NEXT: sra $1, $6, 31 +; 32-NEXT: mtlo $6 +; 32-NEXT: mthi $1 +; 32-NEXT: msub $5, $4 +; 32-NEXT: mfhi $2 +; 32-NEXT: jr $ra +; 32-NEXT: mflo $3 +; +; 32R6-LABEL: msub1: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: mul $1, $5, $4 +; 32R6-NEXT: sltu $2, $6, $1 +; 32R6-NEXT: muh $3, $5, $4 +; 32R6-NEXT: sra $4, $6, 31 +; 32R6-NEXT: subu $3, $4, $3 +; 32R6-NEXT: subu $2, $3, $2 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: subu $3, $6, $1 +; +; DSP-LABEL: msub1: +; DSP: # %bb.0: # %entry +; DSP-NEXT: sra $1, $6, 31 +; DSP-NEXT: mtlo $6, $ac0 +; DSP-NEXT: mthi $1, $ac0 +; DSP-NEXT: msub $ac0, $5, $4 +; DSP-NEXT: mfhi $2, $ac0 +; DSP-NEXT: jr $ra +; DSP-NEXT: mflo $3, $ac0 +; +; 64-LABEL: msub1: +; 64: # %bb.0: # %entry +; 64-NEXT: sll $1, $4, 0 +; 64-NEXT: sll $2, $5, 0 +; 64-NEXT: dmult $2, $1 +; 64-NEXT: mflo $1 +; 64-NEXT: sll $2, $6, 0 +; 64-NEXT: jr $ra +; 64-NEXT: dsubu $2, $2, $1 +; +; 64R6-LABEL: msub1: +; 64R6: # %bb.0: # %entry +; 64R6-NEXT: sll $1, $4, 0 +; 64R6-NEXT: sll $2, $5, 0 +; 64R6-NEXT: dmul $1, $2, $1 +; 64R6-NEXT: sll $2, $6, 0 +; 64R6-NEXT: jr $ra +; 64R6-NEXT: dsubu $2, $2, $1 +; +; 16-LABEL: msub1: +; 16: # %bb.0: # %entry +; 16-NEXT: mult $5, $4 +; 16-NEXT: mflo $2 +; 16-NEXT: mfhi $4 +; 16-NEXT: subu $3, $6, $2 +; 16-NEXT: sltu $6, $2 +; 16-NEXT: move $2, $24 +; 16-NEXT: sra $5, $6, 31 +; 16-NEXT: subu $4, $5, $4 +; 16-NEXT: subu $2, $4, $2 +; 16-NEXT: jrc $ra entry: %conv = sext i32 %c to i64 %conv2 = sext i32 %a to i64 @@ -197,36 +329,61 @@ entry: ret i64 %sub } -; ALL-LABEL: msub2: - -; FIXME: We don't really need this instruction -; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0 -; 32-DAG: mtlo $6 -; 32-DAG: [[m:m]]subu ${{[45]}}, ${{[45]}} -; 32-DAG: [[m]]fhi $2 -; 32-DAG: [[m]]flo $3 - -; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0 -; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] -; DSP-DAG: msubu $[[AC]], ${{[45]}}, ${{[45]}} -; DSP-DAG: mfhi $2, $[[AC]] -; DSP-DAG: mflo $3, $[[AC]] - -; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: sltu $[[T1:[0-9]+]], $6, $[[T0]] -; 32R6-DAG: muhu $[[T2:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: negu $[[T3:[0-9]+]], $[[T2]] -; 32R6-DAG: subu $2, $[[T3]], $[[T1]] -; 32R6-DAG: subu $3, $6, $[[T0]] - -; 64-DAG: d[[m:m]]ult $5, $4 -; 64-DAG: [[m]]flo $[[T0:[0-9]+]] -; 64-DAG: dsubu $2, $6, $[[T0]] - -; 64R6-DAG: dmul $[[T0:[0-9]+]], $5, $4 -; 64R6-DAG: dsubu $2, $6, $[[T0]] - define i64 @msub2(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c) nounwind readnone { +; 32-LABEL: msub2: +; 32: # %bb.0: # %entry +; 32-NEXT: addiu $1, $zero, 0 +; 32-NEXT: mtlo $6 +; 32-NEXT: mthi $1 +; 32-NEXT: msubu $5, $4 +; 32-NEXT: mfhi $2 +; 32-NEXT: jr $ra +; 32-NEXT: mflo $3 +; +; 32R6-LABEL: msub2: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: mul $1, $5, $4 +; 32R6-NEXT: sltu $2, $6, $1 +; 32R6-NEXT: muhu $3, $5, $4 +; 32R6-NEXT: negu $3, $3 +; 32R6-NEXT: subu $2, $3, $2 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: subu $3, $6, $1 +; +; DSP-LABEL: msub2: +; DSP: # %bb.0: # %entry +; DSP-NEXT: addiu $1, $zero, 0 +; DSP-NEXT: mtlo $6, $ac0 +; DSP-NEXT: mthi $1, $ac0 +; DSP-NEXT: msubu $ac0, $5, $4 +; DSP-NEXT: mfhi $2, $ac0 +; DSP-NEXT: jr $ra +; DSP-NEXT: mflo $3, $ac0 +; +; 64-LABEL: msub2: +; 64: # %bb.0: # %entry +; 64-NEXT: dmult $5, $4 +; 64-NEXT: mflo $1 +; 64-NEXT: jr $ra +; 64-NEXT: dsubu $2, $6, $1 +; +; 64R6-LABEL: msub2: +; 64R6: # %bb.0: # %entry +; 64R6-NEXT: dmul $1, $5, $4 +; 64R6-NEXT: jr $ra +; 64R6-NEXT: dsubu $2, $6, $1 +; +; 16-LABEL: msub2: +; 16: # %bb.0: # %entry +; 16-NEXT: multu $5, $4 +; 16-NEXT: mflo $2 +; 16-NEXT: mfhi $4 +; 16-NEXT: subu $3, $6, $2 +; 16-NEXT: sltu $6, $2 +; 16-NEXT: move $2, $24 +; 16-NEXT: neg $4, $4 +; 16-NEXT: subu $2, $4, $2 +; 16-NEXT: jrc $ra entry: %conv = zext i32 %c to i64 %conv2 = zext i32 %a to i64 @@ -236,40 +393,63 @@ entry: ret i64 %sub } -; ALL-LABEL: msub3: - -; FIXME: We don't really need this instruction -; 32-DAG: mthi $6 -; 32-DAG: mtlo $7 -; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}} -; 32-DAG: [[m]]fhi $2 -; 32-DAG: [[m]]flo $3 - -; DSP-DAG: mtlo $7, $[[AC:ac[0-3]+]] -; DSP-DAG: mthi $6, $[[AC]] -; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}} -; DSP-DAG: mfhi $2, $[[AC]] -; DSP-DAG: mflo $3, $[[AC]] - -; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: sltu $[[T1:[0-9]+]], $7, $[[T0]] -; 32R6-DAG: muh $[[T2:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: subu $[[T3:[0-9]+]], $6, $[[T2]] -; 32R6-DAG: subu $2, $[[T3]], $[[T1]] -; 32R6-DAG: subu $3, $7, $[[T0]] - -; 64-DAG: sll $[[T0:[0-9]+]], $4, 0 -; 64-DAG: sll $[[T1:[0-9]+]], $5, 0 -; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]] -; 64-DAG: [[m]]flo $[[T2:[0-9]+]] -; 64-DAG: dsubu $2, $6, $[[T2]] - -; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0 -; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0 -; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]] -; 64R6-DAG: dsubu $2, $6, $[[T2]] - define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone { +; 32-LABEL: msub3: +; 32: # %bb.0: # %entry +; 32-NEXT: mtlo $7 +; 32-NEXT: mthi $6 +; 32-NEXT: msub $5, $4 +; 32-NEXT: mfhi $2 +; 32-NEXT: jr $ra +; 32-NEXT: mflo $3 +; +; 32R6-LABEL: msub3: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: mul $1, $5, $4 +; 32R6-NEXT: sltu $2, $7, $1 +; 32R6-NEXT: muh $3, $5, $4 +; 32R6-NEXT: subu $3, $6, $3 +; 32R6-NEXT: subu $2, $3, $2 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: subu $3, $7, $1 +; +; DSP-LABEL: msub3: +; DSP: # %bb.0: # %entry +; DSP-NEXT: mtlo $7, $ac0 +; DSP-NEXT: mthi $6, $ac0 +; DSP-NEXT: msub $ac0, $5, $4 +; DSP-NEXT: mfhi $2, $ac0 +; DSP-NEXT: jr $ra +; DSP-NEXT: mflo $3, $ac0 +; +; 64-LABEL: msub3: +; 64: # %bb.0: # %entry +; 64-NEXT: sll $1, $4, 0 +; 64-NEXT: sll $2, $5, 0 +; 64-NEXT: dmult $2, $1 +; 64-NEXT: mflo $1 +; 64-NEXT: jr $ra +; 64-NEXT: dsubu $2, $6, $1 +; +; 64R6-LABEL: msub3: +; 64R6: # %bb.0: # %entry +; 64R6-NEXT: sll $1, $4, 0 +; 64R6-NEXT: sll $2, $5, 0 +; 64R6-NEXT: dmul $1, $2, $1 +; 64R6-NEXT: jr $ra +; 64R6-NEXT: dsubu $2, $6, $1 +; +; 16-LABEL: msub3: +; 16: # %bb.0: # %entry +; 16-NEXT: mult $5, $4 +; 16-NEXT: mflo $2 +; 16-NEXT: mfhi $4 +; 16-NEXT: subu $3, $7, $2 +; 16-NEXT: sltu $7, $2 +; 16-NEXT: move $2, $24 +; 16-NEXT: subu $4, $6, $4 +; 16-NEXT: subu $2, $4, $2 +; 16-NEXT: jrc $ra entry: %conv = sext i32 %a to i64 %conv3 = sext i32 %b to i64 @@ -278,10 +458,49 @@ entry: ret i64 %sub } -; ALL-LABEL: msub4 -; ALL-NOT: msub ${{[0-9]+}}, ${{[0-9]+}} - define i32 @msub4(i32 %a, i32 %b, i32 %c) { +; 32-LABEL: msub4: +; 32: # %bb.0: # %entry +; 32-NEXT: mul $1, $4, $5 +; 32-NEXT: jr $ra +; 32-NEXT: subu $2, $6, $1 +; +; 32R6-LABEL: msub4: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: mul $1, $4, $5 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: subu $2, $6, $1 +; +; DSP-LABEL: msub4: +; DSP: # %bb.0: # %entry +; DSP-NEXT: mul $1, $4, $5 +; DSP-NEXT: jr $ra +; DSP-NEXT: subu $2, $6, $1 +; +; 64-LABEL: msub4: +; 64: # %bb.0: # %entry +; 64-NEXT: sll $1, $5, 0 +; 64-NEXT: sll $2, $4, 0 +; 64-NEXT: mul $1, $2, $1 +; 64-NEXT: sll $2, $6, 0 +; 64-NEXT: jr $ra +; 64-NEXT: subu $2, $2, $1 +; +; 64R6-LABEL: msub4: +; 64R6: # %bb.0: # %entry +; 64R6-NEXT: sll $1, $5, 0 +; 64R6-NEXT: sll $2, $4, 0 +; 64R6-NEXT: mul $1, $2, $1 +; 64R6-NEXT: sll $2, $6, 0 +; 64R6-NEXT: jr $ra +; 64R6-NEXT: subu $2, $2, $1 +; +; 16-LABEL: msub4: +; 16: # %bb.0: # %entry +; 16-NEXT: mult $4, $5 +; 16-NEXT: mflo $2 +; 16-NEXT: subu $2, $6, $2 +; 16-NEXT: jrc $ra entry: %mul = mul nsw i32 %a, %b %sub = sub nsw i32 %c, %mul -- 2.11.0