From 443d5e3973e8e774addd830bc1091498b49b4bf2 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Thu, 4 Oct 2018 08:18:14 -0700 Subject: [PATCH] drm/i915/icl: MBUS B credit change No functional change. But just a minor change to keep up with Spec, since it has changed since commit c3cc39c539d4 ("drm/i915/icl: program mbus during pipe enable") The instructions previously said to program pipe's B credit = 24 / number of pipes, which is 8 for ICL. Now the spec gives us direct values independent of number of pipes. Let's keep in sync. Also just a reorder on fields to make easier to compare against spec's sequence: A -> BW -> B. Cc: Lucas De Marchi Cc: Paulo Zanoni Cc: Mahesh Kumar Cc: Arthur J Runyan Signed-off-by: Rodrigo Vivi Reviewed-by: Mahesh Kumar Reviewed-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20181004151814.6054-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_display.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e2e8420b17cc..1aefbc9347a6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5694,10 +5694,9 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc) enum pipe pipe = crtc->pipe; uint32_t val; - val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2); - - /* Program B credit equally to all pipes */ - val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes); + val = MBUS_DBOX_A_CREDIT(2); + val |= MBUS_DBOX_BW_CREDIT(1); + val |= MBUS_DBOX_B_CREDIT(8); I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); } -- 2.11.0