From 447f15ac4236e37113ed8cbeb872227f19e95c01 Mon Sep 17 00:00:00 2001 From: "astoria-d@fc" Date: Thu, 8 Sep 2016 21:24:32 +0900 Subject: [PATCH] rtl sim started... --- de0_cv_nes/chip_selector.vhd | 89 +++++++++++++++ de0_cv_nes/de0_cv_nes.qsf | 5 +- de0_cv_nes/de0_cv_nes.vhd | 127 +++++++++------------ de0_cv_nes/dummy-mos6502.vhd | 4 +- .../simulation/modelsim/de0_cv_nes_modelsim.mpf | 2 +- .../modelsim/de0_cv_nes_run_msim_rtl_vhdl.do | 12 +- 6 files changed, 163 insertions(+), 76 deletions(-) create mode 100644 de0_cv_nes/chip_selector.vhd diff --git a/de0_cv_nes/chip_selector.vhd b/de0_cv_nes/chip_selector.vhd new file mode 100644 index 0000000..72628bb --- /dev/null +++ b/de0_cv_nes/chip_selector.vhd @@ -0,0 +1,89 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity chip_selector is + port ( + pi_rst_n : in std_logic; + pi_base_clk : in std_logic; + po_cpu_en : out std_logic_vector (7 downto 0); + po_ppu_en : out std_logic_vector (3 downto 0) + ); +end chip_selector; + +architecture rtl of chip_selector is + +signal reg_cpu_en : std_logic_vector (7 downto 0); +signal reg_ppu_en : std_logic_vector (3 downto 0); + +begin + --Actual NES base clock = 21.477272 MHz + --CPU clock = base clock / 12 + --PPU clock = base clock / 4 + --Actual NES CPU clock = 1.78 MHz (559 ns / cycle) + --VGA clock = 25 MHz. + + ---DE1 base clock 50 MHz + ---motones sim project uses following clock. + --cpu clock = base clock / 16 + --ppu clock = base clock / 8 + --vga clock = base clock / 2 + --emu ppu clock = base clock / 4 + + po_cpu_en <= reg_cpu_en; + po_ppu_en <= reg_ppu_en; + + cpu_clk_p : process (pi_rst_n, pi_base_clk) + variable ref_cnt : integer range 0 to 15; + begin + if (pi_rst_n = '0') then + reg_cpu_en <= (others => '0'); + ref_cnt := 0; + else + if (rising_edge(pi_base_clk)) then + if (ref_cnt = 0) then + reg_cpu_en <= "00000001"; + elsif (ref_cnt = 3) then + reg_cpu_en <= "00000010"; + elsif (ref_cnt = 7) then + reg_cpu_en <= "00000100"; + elsif (ref_cnt = 11) then + reg_cpu_en <= "00001000"; + elsif (ref_cnt = 15) then + reg_cpu_en <= "00010000"; + elsif (ref_cnt = 19) then + reg_cpu_en <= "00100000"; + elsif (ref_cnt = 23) then + reg_cpu_en <= "01000000"; + elsif (ref_cnt = 27) then + reg_cpu_en <= "10000000"; + end if; + ref_cnt := ref_cnt + 1; + end if; + end if; + end process; + + ppu_clk_p : process (pi_rst_n, pi_base_clk) + variable ref_cnt : integer range 0 to 31; + begin + if (pi_rst_n = '0') then + reg_ppu_en <= (others => '0'); + ref_cnt := 0; + else + if (rising_edge(pi_base_clk)) then + if (ref_cnt = 0) then + reg_ppu_en <= "0001"; + elsif (ref_cnt = 3) then + reg_ppu_en <= "0010"; + elsif (ref_cnt = 7) then + reg_ppu_en <= "0100"; + elsif (ref_cnt = 11) then + reg_ppu_en <= "1000"; + end if; + ref_cnt := ref_cnt + 1; + end if; + end if; + end process; + +end rtl; + diff --git a/de0_cv_nes/de0_cv_nes.qsf b/de0_cv_nes/de0_cv_nes.qsf index f36f093..d450833 100644 --- a/de0_cv_nes/de0_cv_nes.qsf +++ b/de0_cv_nes/de0_cv_nes.qsf @@ -94,9 +94,12 @@ set_location_assignment PIN_AB12 -to nt_v_mirror #project files -set_global_assignment -name VHDL_FILE de0_cv_nes.vhd + +set_global_assignment -name VHDL_FILE chip_selector.vhd set_global_assignment -name VHDL_FILE dummy-mos6502.vhd +set_global_assignment -name VHDL_FILE de0_cv_nes.vhd + ##timing definition... set_global_assignment -name SDC_FILE mos6502-timing.sdc diff --git a/de0_cv_nes/de0_cv_nes.vhd b/de0_cv_nes/de0_cv_nes.vhd index 025218b..e2fe7b2 100644 --- a/de0_cv_nes/de0_cv_nes.vhd +++ b/de0_cv_nes/de0_cv_nes.vhd @@ -30,6 +30,7 @@ architecture rtl of de0_cv_nes is component mos6502 port ( pi_base_clk : in std_logic; + pi_cpu_en : in std_logic_vector (7 downto 0); pi_rdy : in std_logic; pi_rst_n : in std_logic; pi_irq_n : in std_logic; @@ -40,90 +41,76 @@ architecture rtl of de0_cv_nes is ); end component; - component clock_divider - port ( base_clk : in std_logic; - reset_n : in std_logic; - cpu_clk : out std_logic; - ppu_clk : out std_logic; - emu_ppu_clk : out std_logic; - vga_clk : out std_logic; - cpu_mem_clk : out std_logic; - cpu_recv_clk : out std_logic; - emu_ppu_mem_clk : out std_logic - ); - end component; - - component address_decoder - port ( - addr : in std_logic_vector (15 downto 0); - rom_ce_n : out std_logic; - ram_ce_n : out std_logic; - ppu_ce_n : out std_logic; - apu_ce_n : out std_logic - ); - end component; - - component ram - generic (abus_size : integer := 16; dbus_size : integer := 8); - port ( - clk : in std_logic; - ce_n, oe_n, we_n : in std_logic; --select pin active low. - addr : in std_logic_vector (abus_size - 1 downto 0); - d_io : inout std_logic_vector (dbus_size - 1 downto 0) - ); - end component; - - component rom - generic (abus_size : integer := 15; dbus_size : integer := 8); - port ( - clk : in std_logic; - ce_n : in std_logic; --active low. - addr : in std_logic_vector (abus_size - 1 downto 0); - data : out std_logic_vector (dbus_size - 1 downto 0) - ); - end component; - + component chip_selector + port ( + pi_rst_n : in std_logic; + pi_base_clk : in std_logic; + po_cpu_en : out std_logic_vector (7 downto 0); + po_ppu_en : out std_logic_vector (3 downto 0) + ); + end component; + component ppu port ( - base_clk : in std_logic; - ce_n : in std_logic; - rst_n : in std_logic; - r_nw : in std_logic; - cpu_addr : in std_logic_vector (2 downto 0); - cpu_d : inout std_logic_vector (7 downto 0); + pi_base_clk : in std_logic; + pi_ce_n : in std_logic; + pi_rst_n : in std_logic; + pi_r_nw : in std_logic; + pi_cpu_addr : in std_logic_vector (2 downto 0); + pio_cpu_d : inout std_logic_vector (7 downto 0); - rd_n : out std_logic; - wr_n : out std_logic; - ale_n : out std_logic; - vram_addr : out std_logic_vector (13 downto 0); - vram_data : inout std_logic_vector (7 downto 0) + po_rd_n : out std_logic; + po_wr_n : out std_logic; + po_ale_n : out std_logic; + po_vram_addr : out std_logic_vector (13 downto 0); + pio_vram_data : inout std_logic_vector (7 downto 0) ); end component; component v_address_decoder port ( - v_addr : in std_logic_vector (13 downto 0); - nt_v_mirror : in std_logic; - pt_ce_n : out std_logic; - nt0_ce_n : out std_logic; - nt1_ce_n : out std_logic + pi_v_addr : in std_logic_vector (13 downto 0); + pi_nt_v_mirror : in std_logic; + po_pt_ce_n : out std_logic; + po_nt0_ce_n : out std_logic; + po_nt1_ce_n : out std_logic ); end component; - - component apu - port ( clk : in std_logic; - ce_n : in std_logic; - rst_n : in std_logic; - r_nw : inout std_logic; - cpu_addr : inout std_logic_vector (15 downto 0); - cpu_d : inout std_logic_vector (7 downto 0); - rdy : out std_logic - ); - end component; + +signal wr_cpu_en : std_logic_vector (7 downto 0); +signal wr_ppu_en : std_logic_vector (3 downto 0); + +signal wr_rdy : std_logic; +signal wr_irq_n : std_logic; +signal wr_nmi_n : std_logic; +signal wr_r_nw : std_logic; + +signal wr_addr : std_logic_vector ( 15 downto 0); +signal wr_d_io : std_logic_vector ( 7 downto 0); begin dbg_base_clk <= pi_base_clk; + chip_selector_inst : chip_selector port map + (pi_rst_n, pi_base_clk, wr_cpu_en, wr_ppu_en); + + --mos 6502 cpu instance + cpu_inst : mos6502 port map ( + pi_base_clk, + wr_cpu_en, + wr_rdy, + pi_rst_n, + wr_irq_n, + wr_nmi_n, + wr_r_nw, + wr_addr, + wr_d_io + ); + + wr_rdy <= '0'; + wr_irq_n <= '0'; + wr_nmi_n <= '0'; + po_h_sync_n <= '0'; po_v_sync_n <= '0'; po_r <= (others => '0'); diff --git a/de0_cv_nes/dummy-mos6502.vhd b/de0_cv_nes/dummy-mos6502.vhd index 5435b49..19ab7de 100644 --- a/de0_cv_nes/dummy-mos6502.vhd +++ b/de0_cv_nes/dummy-mos6502.vhd @@ -4,6 +4,7 @@ use ieee.std_logic_1164.all; entity mos6502 is port ( pi_base_clk : in std_logic; + pi_cpu_en : in std_logic_vector (7 downto 0); pi_rdy : in std_logic; pi_rst_n : in std_logic; pi_irq_n : in std_logic; @@ -79,7 +80,7 @@ end; ref_cnt := 0; elsif (rising_edge(pi_base_clk)) then - + if (pi_cpu_en(0) = '1') then if (pi_rdy = '1') then if (init_done = '0') then if (global_step_cnt = 0) then @@ -516,6 +517,7 @@ end; po_addr <= (others => 'Z'); pio_d_io <= (others => 'Z'); end if;--if (rdy = '1') then + end if;--if (pi_cpu_en(0) = '1') then end if; --if (rst_n = '0') then end process; diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_modelsim.mpf b/de0_cv_nes/simulation/modelsim/de0_cv_nes_modelsim.mpf index ddf41e2..efc4187 100644 --- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_modelsim.mpf +++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_modelsim.mpf @@ -3,7 +3,7 @@ others = $MODEL_TECH/../modelsim.ini ; Altera specific primitive library mappings -work = gate_work +work = rtl_work [vcom] ; Turn on VHDL-1993 as the default. Normally is off. ; VHDL93 = 1 diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do index e87d9a1..bc1eabb 100644 --- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do +++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do @@ -6,6 +6,7 @@ vlib rtl_work vmap work rtl_work vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de0_cv_nes/de0_cv_nes.vhd} +vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de0_cv_nes/chip_selector.vhd} vcom -93 -work work {C:/Users/motooka/Documents/001-proj/999.my-proj/001.nes-fpga/repo/motonesfpga/de0_cv_nes/testbench_motones_sim.vhd} @@ -14,15 +15,20 @@ vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev - ##script custom part... -add wave -label rst_n sim:/testbench_motones_sim/sim_board/rst_n; -add wave -label r_nw sim:/testbench_motones_sim/sim_board/r_nw; +#add wave -label rst_n sim:/testbench_motones_sim/sim_board/pi_rst_n; +#add wave -label r_nw sim:/testbench_motones_sim/sim_board/wr_r_nw; +#add wave -label base_clk sim:/testbench_motones_sim/sim_board/pi_base_clk; + +#add wave sim:/testbench_motones_sim/*; +#add wave sim:/testbench_motones_sim/sim_board/*; +add wave sim:/testbench_motones_sim/sim_board/chip_selector_inst/*; view structure view signals run 8 us +run 100 us wave zoom full -#run 430 us -- 2.11.0