From 455e169d7cad4499ed9f4647215b9ec71aa706e4 Mon Sep 17 00:00:00 2001 From: Taylor Simpson Date: Thu, 27 Apr 2023 16:00:03 -0700 Subject: [PATCH] Hexagon (target/hexagon) Short-circuit packet predicate writes In certain cases, we can avoid the overhead of writing to hex_new_pred_value and write directly to hex_pred. We consider predicate reads/writes when computing ctx->need_commit. The get_result_pred() function uses this field to decide between hex_new_pred_value and hex_pred. Then, we can early-exit from gen_pred_writes. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-13-tsimpson@quicinc.com> --- target/hexagon/genptr.c | 15 ++++++++++++--- target/hexagon/genptr.h | 1 + target/hexagon/translate.c | 14 +++++++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 9858d7bc35..5025e172cf 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -110,8 +110,18 @@ static void gen_log_reg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 val) gen_log_reg_write(ctx, rnum + 1, val32); } +TCGv get_result_pred(DisasContext *ctx, int pnum) +{ + if (ctx->need_commit) { + return hex_new_pred_value[pnum]; + } else { + return hex_pred[pnum]; + } +} + void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) { + TCGv pred = get_result_pred(ctx, pnum); TCGv base_val = tcg_temp_new(); tcg_gen_andi_tl(base_val, val, 0xff); @@ -124,10 +134,9 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) * straight assignment. Otherwise, do an and. */ if (!test_bit(pnum, ctx->pregs_written)) { - tcg_gen_mov_tl(hex_new_pred_value[pnum], base_val); + tcg_gen_mov_tl(pred, base_val); } else { - tcg_gen_and_tl(hex_new_pred_value[pnum], - hex_new_pred_value[pnum], base_val); + tcg_gen_and_tl(pred, pred, base_val); } if (HEX_DEBUG) { tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 420867f934..e11ccc2358 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -35,6 +35,7 @@ void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot); void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot); TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); +TCGv get_result_pred(DisasContext *ctx, int pnum); void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val); void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val); void gen_set_usr_field(DisasContext *ctx, int field, TCGv val); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 6fa885cf16..bcf64f725a 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -386,6 +386,14 @@ static bool need_commit(DisasContext *ctx) } } + /* Check for overlap between predicate reads and writes */ + for (int i = 0; i < ctx->preg_log_idx; i++) { + int pnum = ctx->preg_log[i]; + if (test_bit(pnum, ctx->pregs_read)) { + return true; + } + } + return false; } @@ -503,7 +511,7 @@ static void gen_start_packet(DisasContext *ctx) * Preload the predicated pred registers into hex_new_pred_value[pred_num] * Only endloop instructions conditionally write to pred registers */ - if (pkt->pkt_has_endloop) { + if (ctx->need_commit && pkt->pkt_has_endloop) { for (int i = 0; i < ctx->preg_log_idx; i++) { int pred_num = ctx->preg_log[i]; tcg_gen_mov_tl(hex_new_pred_value[pred_num], hex_pred[pred_num]); @@ -622,8 +630,8 @@ static void gen_reg_writes(DisasContext *ctx) static void gen_pred_writes(DisasContext *ctx) { - /* Early exit if the log is empty */ - if (!ctx->preg_log_idx) { + /* Early exit if not needed or the log is empty */ + if (!ctx->need_commit || !ctx->preg_log_idx) { return; } -- 2.11.0