From 4629e0da6a19ea5883ecdfca841cacb3de657d73 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 2 Sep 2013 12:00:53 +0000 Subject: [PATCH] FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189755 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/h-register-addressing-32.ll | 23 ++++++++++++++++++++++- test/CodeGen/X86/h-register-addressing-64.ll | 23 ++++++++++++++++++++++- test/CodeGen/X86/h-registers-1.ll | 15 ++++++++++++--- 3 files changed, 56 insertions(+), 5 deletions(-) diff --git a/test/CodeGen/X86/h-register-addressing-32.ll b/test/CodeGen/X86/h-register-addressing-32.ll index 3cf2db36970..68e8c605f67 100644 --- a/test/CodeGen/X86/h-register-addressing-32.ll +++ b/test/CodeGen/X86/h-register-addressing-32.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=-bmi | grep "movzbl %[abcd]h," | count 7 +; RUN: llc < %s -march=x86 -mattr=-bmi | FileCheck %s ; Use h-register extract and zero-extend. @@ -9,6 +9,9 @@ define double @foo8(double* nocapture inreg %p, i32 inreg %x) nounwind readonly %t3 = load double* %t2, align 8 ret double %t3 } +; CHECK: foo8: +; CHECK: movzbl %{{[abcd]}}h, %e + define float @foo4(float* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t0 = lshr i32 %x, 8 %t1 = and i32 %t0, 255 @@ -16,6 +19,9 @@ define float @foo4(float* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t3 = load float* %t2, align 8 ret float %t3 } +; CHECK: foo4: +; CHECK: movzbl %{{[abcd]}}h, %e + define i16 @foo2(i16* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t0 = lshr i32 %x, 8 %t1 = and i32 %t0, 255 @@ -23,6 +29,9 @@ define i16 @foo2(i16* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t3 = load i16* %t2, align 8 ret i16 %t3 } +; CHECK: foo2: +; CHECK: movzbl %{{[abcd]}}h, %e + define i8 @foo1(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t0 = lshr i32 %x, 8 %t1 = and i32 %t0, 255 @@ -30,6 +39,9 @@ define i8 @foo1(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t3 = load i8* %t2, align 8 ret i8 %t3 } +; CHECK: foo1: +; CHECK: movzbl %{{[abcd]}}h, %e + define i8 @bar8(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t0 = lshr i32 %x, 5 %t1 = and i32 %t0, 2040 @@ -37,6 +49,9 @@ define i8 @bar8(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t3 = load i8* %t2, align 8 ret i8 %t3 } +; CHECK: bar8: +; CHECK: movzbl %{{[abcd]}}h, %e + define i8 @bar4(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t0 = lshr i32 %x, 6 %t1 = and i32 %t0, 1020 @@ -44,6 +59,9 @@ define i8 @bar4(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t3 = load i8* %t2, align 8 ret i8 %t3 } +; CHECK: bar4: +; CHECK: movzbl %{{[abcd]}}h, %e + define i8 @bar2(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t0 = lshr i32 %x, 7 %t1 = and i32 %t0, 510 @@ -51,3 +69,6 @@ define i8 @bar2(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly { %t3 = load i8* %t2, align 8 ret i8 %t3 } +; CHECK: bar2: +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: ret diff --git a/test/CodeGen/X86/h-register-addressing-64.ll b/test/CodeGen/X86/h-register-addressing-64.ll index 07cdc5df594..3f549d26c2f 100644 --- a/test/CodeGen/X86/h-register-addressing-64.ll +++ b/test/CodeGen/X86/h-register-addressing-64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=-bmi | grep "movzbl %[abcd]h," | count 7 +; RUN: llc < %s -march=x86-64 -mattr=-bmi | FileCheck %s ; Use h-register extract and zero-extend. @@ -9,6 +9,9 @@ define double @foo8(double* nocapture inreg %p, i64 inreg %x) nounwind readonly %t3 = load double* %t2, align 8 ret double %t3 } +; CHECK: foo8: +; CHECK: movzbl %{{[abcd]}}h, %e + define float @foo4(float* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t0 = lshr i64 %x, 8 %t1 = and i64 %t0, 255 @@ -16,6 +19,9 @@ define float @foo4(float* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t3 = load float* %t2, align 8 ret float %t3 } +; CHECK: foo4: +; CHECK: movzbl %{{[abcd]}}h, %e + define i16 @foo2(i16* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t0 = lshr i64 %x, 8 %t1 = and i64 %t0, 255 @@ -23,6 +29,9 @@ define i16 @foo2(i16* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t3 = load i16* %t2, align 8 ret i16 %t3 } +; CHECK: foo2: +; CHECK: movzbl %{{[abcd]}}h, %e + define i8 @foo1(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t0 = lshr i64 %x, 8 %t1 = and i64 %t0, 255 @@ -30,6 +39,9 @@ define i8 @foo1(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t3 = load i8* %t2, align 8 ret i8 %t3 } +; CHECK: foo1: +; CHECK: movzbl %{{[abcd]}}h, %e + define i8 @bar8(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t0 = lshr i64 %x, 5 %t1 = and i64 %t0, 2040 @@ -37,6 +49,9 @@ define i8 @bar8(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t3 = load i8* %t2, align 8 ret i8 %t3 } +; CHECK: bar8: +; CHECK: movzbl %{{[abcd]}}h, %e + define i8 @bar4(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t0 = lshr i64 %x, 6 %t1 = and i64 %t0, 1020 @@ -44,6 +59,9 @@ define i8 @bar4(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t3 = load i8* %t2, align 8 ret i8 %t3 } +; CHECK: bar4: +; CHECK: movzbl %{{[abcd]}}h, %e + define i8 @bar2(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t0 = lshr i64 %x, 7 %t1 = and i64 %t0, 510 @@ -51,3 +69,6 @@ define i8 @bar2(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly { %t3 = load i8* %t2, align 8 ret i8 %t3 } +; CHECK: bar2: +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: ret diff --git a/test/CodeGen/X86/h-registers-1.ll b/test/CodeGen/X86/h-registers-1.ll index 9d38172fa91..7254325a926 100644 --- a/test/CodeGen/X86/h-registers-1.ll +++ b/test/CodeGen/X86/h-registers-1.ll @@ -1,12 +1,21 @@ -; RUN: llc -mattr=-bmi < %s -mtriple=x86_64-linux > %t -; RUN: grep "movzbl %[abcd]h," %t | count 8 -; RUN: grep "%[abcd]h" %t | not grep "%r[[:digit:]]*d" +; RUN: llc -mattr=-bmi < %s -mtriple=x86_64-linux | FileCheck %s ; LLVM creates virtual registers for values live across blocks ; based on the type of the value. Make sure that the extracts ; here use the GR64_NOREX register class for their result, ; instead of plain GR64. +; CHECK: foo: +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: movzbl %{{[abcd]}}h, %e +; CHECK: ret + define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) { %sa = lshr i64 %a, 8 -- 2.11.0