From 47101319272c19d0b9987ebb569d8ff1cbbdeafc Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Mar 2019 16:12:26 +0000 Subject: [PATCH] MIR: Freeze reserved regs after parsing everything The AMDGPU implementation of getReservedRegs depends on MachineFunctionInfo fields that are parsed from the YAML section. This was reserving the wrong register since it was setting the reserved regs before parsing the correct one. Some tests were relying on the default reserved set for the assumed default calling convention. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357083 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MIRParser/MIRParser.cpp | 11 +++++--- .../AMDGPU/GlobalISel/regbankselect-phi.mir | 4 +-- test/CodeGen/AMDGPU/endpgm-dce.mir | 1 + test/CodeGen/AMDGPU/misched-killflags.mir | 10 +++++--- .../rename-independent-subregs-mac-operands.mir | 12 +++++++-- .../MIR/AMDGPU/parse-order-reserved-regs.mir | 29 ++++++++++++++++++++++ 6 files changed, 57 insertions(+), 10 deletions(-) create mode 100644 test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir diff --git a/lib/CodeGen/MIRParser/MIRParser.cpp b/lib/CodeGen/MIRParser/MIRParser.cpp index 3598cbe22ce..74d308de8bd 100644 --- a/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/lib/CodeGen/MIRParser/MIRParser.cpp @@ -426,6 +426,14 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF, } } + // Set the reserved registers after parsing MachineFuncInfo. The target may + // have been recording information used to select the reserved registers + // there. + // FIXME: This is a temporary workaround until the reserved registers can be + // serialized. + MachineRegisterInfo &MRI = MF.getRegInfo(); + MRI.freezeReservedRegs(MF); + computeFunctionProperties(MF); MF.getSubtarget().mirFileLoaded(MF); @@ -564,9 +572,6 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS, } } - // FIXME: This is a temporary workaround until the reserved registers can be - // serialized. - MRI.freezeReservedRegs(MF); return Error; } diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir index c165a79f063..1a98cbec8d5 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir @@ -1075,7 +1075,7 @@ body: | ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] @@ -1097,7 +1097,7 @@ body: | %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 - %2:_(s32) = COPY $sgpr1 + %2:_(s32) = COPY $sgpr0 %3:_(s32) = G_CONSTANT i32 0 %4:_(s1) = G_TRUNC %0 %5:_(s1) = G_ICMP intpred(eq), %2, %3 diff --git a/test/CodeGen/AMDGPU/endpgm-dce.mir b/test/CodeGen/AMDGPU/endpgm-dce.mir index 009855014bf..3be9248e2df 100644 --- a/test/CodeGen/AMDGPU/endpgm-dce.mir +++ b/test/CodeGen/AMDGPU/endpgm-dce.mir @@ -112,6 +112,7 @@ name: call tracksRegLiveness: true body: | bb.0: + liveins: $sgpr2_sgpr3 $vcc = IMPLICIT_DEF $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3 diff --git a/test/CodeGen/AMDGPU/misched-killflags.mir b/test/CodeGen/AMDGPU/misched-killflags.mir index 0595edf894c..bef38d20c5e 100644 --- a/test/CodeGen/AMDGPU/misched-killflags.mir +++ b/test/CodeGen/AMDGPU/misched-killflags.mir @@ -3,9 +3,13 @@ --- name: func0 tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true + scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' + scratchWaveOffsetReg: '$sgpr7' + frameOffsetReg: '$sgpr7' body: | bb.0: - liveins: $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3 $sgpr33 = S_MOV_B32 $sgpr7 $sgpr32 = S_MOV_B32 $sgpr33 @@ -29,7 +33,7 @@ body: | # CHECK-DAG: $sgpr10 = S_MOV_B32 5 # CHECK-DAG: $sgpr9 = S_MOV_B32 4 # CHECK-DAG: $sgpr8 = S_MOV_B32 3 -# CHECK-DAG: $sgpr33 = S_MOV_B32 killed $sgpr7 +# CHECK-DAG: $sgpr33 = S_MOV_B32 $sgpr7 # CHECK: $vgpr0 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $sgpr8_sgpr9_sgpr10_sgpr11 # CHECK: $sgpr32 = S_MOV_B32 $sgpr33 # CHECK: BUNDLE implicit-def $sgpr6_sgpr7, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $scc { @@ -41,5 +45,5 @@ body: | # CHECK: $vgpr1 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11 # CHECK: $vgpr2 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11 # CHECK: $vgpr3 = V_MOV_B32_e32 killed $sgpr11, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec -# CHECK: S_NOP 0, implicit killed $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 +# CHECK: S_NOP 0, implicit $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 # CHECK: S_ENDPGM 0 diff --git a/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir b/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir index 1dbf5de2715..2f4b0fd02fe 100644 --- a/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir +++ b/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir @@ -11,6 +11,11 @@ legalized: false regBankSelected: false selected: false tracksRegLiveness: true +machineFunctionInfo: + scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' + scratchWaveOffsetReg: '$sgpr4' + frameOffsetReg: '$sgpr4' + registers: - { id: 0, class: vreg_128 } - { id: 1, class: vreg_128 } @@ -92,6 +97,10 @@ legalized: false regBankSelected: false selected: false tracksRegLiveness: true +machineFunctionInfo: + scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' + scratchWaveOffsetReg: '$sgpr4' + frameOffsetReg: '$sgpr4' registers: - { id: 0, class: vgpr_32, preferred-register: '' } - { id: 1, class: vgpr_32, preferred-register: '' } @@ -130,8 +139,7 @@ body: | BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN %6.sub0, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $sgpr30_sgpr31 = COPY %5 - $sgpr5 = COPY $sgpr5 - S_SETPC_B64_return $sgpr30_sgpr31, implicit $sgpr5 + S_SETPC_B64_return $sgpr30_sgpr31 ... diff --git a/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir b/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir new file mode 100644 index 00000000000..fc72e21b82b --- /dev/null +++ b/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir @@ -0,0 +1,29 @@ +# RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s + +# Previously getReservedRegs was called before parsing +# machineFunctionInfo, but the AMDGPU implementation depends on +# setting register fields to reserve there. $sgpr50 would then not be +# reserved, resulting in a verifier error from an undefined register. + +--- +# CHECK: machineFunctionInfo: +# CHECK: isEntryFunction: true +# CHECK: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' +# CHECK: scratchWaveOffsetReg: '$sgpr50' +# CHECK: frameOffsetReg: '$sgpr50' +# CHECK: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, implicit $exec :: (load 4, addrspace 5) +name: reserve_correct_register +tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true + scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' + scratchWaveOffsetReg: '$sgpr50' + frameOffsetReg: '$sgpr50' +stack: + - { id: 0, type: default, offset: 0, size: 4, alignment: 4 } + +body: | + bb.0: + renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, implicit $exec :: (load 4, addrspace 5) + S_ENDPGM 0 +... -- 2.11.0