From 481ecf26d0de1ddc401d80515e2e2dd79e2e26a8 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 5 Sep 2016 06:43:00 +0000 Subject: [PATCH] [Target] Remove the AvailableRegClasses vector from TargetLoweringBase. It was a private member with no code reading from it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280647 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetLowering.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 052b704ef29..93bdeaaff0e 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -1409,15 +1409,12 @@ protected: /// that class natively. void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); - AvailableRegClasses.push_back(std::make_pair(VT, RC)); RegClassForVT[VT.SimpleTy] = RC; } /// Remove all register classes. void clearRegisterClasses() { std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); - - AvailableRegClasses.clear(); } /// \brief Remove all operation actions. @@ -2064,7 +2061,6 @@ private: LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const; private: - std::vector > AvailableRegClasses; /// Targets can specify ISD nodes that they would like PerformDAGCombine /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this -- 2.11.0