From 488460b4152924659d24d4a8e7043ec4568a4738 Mon Sep 17 00:00:00 2001 From: Prasad Sodagudi Date: Tue, 28 Jul 2015 10:01:04 +0530 Subject: [PATCH] ARM: dts: msm: Add qcom,dump-size entry for dumping CPU L1/L2 caches Update arm cache documentation about qcom,dump-size to dump the CPU L1/L2 caches in order to analyze data corruption. Change-Id: Ia9350b9c7810db7eb900957b4ce5dac046ab5e0d Signed-off-by: Abhimanyu Kapur Signed-off-by: Patrick Daly Signed-off-by: Prasad Sodagudi --- Documentation/devicetree/bindings/arm/cache.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt index b27cedf485f8..a9594f026506 100644 --- a/Documentation/devicetree/bindings/arm/cache.txt +++ b/Documentation/devicetree/bindings/arm/cache.txt @@ -64,6 +64,14 @@ This document provides the device tree bindings for ARM architected caches. bindings of power controller specified by the phandle [5]. + - qcom,dump-size + Usage: Optional + Value type: + Definition: The memory size needed to contain a copy of the + cache data and associated tag ram. + size = nways * nsets * (bytes per cache line + + bytes tag ram per line) + Example(dual-cluster big.LITTLE system 32-bit) cpus { -- 2.11.0