From 48ff5ffe9e2a90f853ce3645b1b97ea7885eccf1 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 19 Aug 2011 18:49:59 +0000 Subject: [PATCH] Thumb assembly parsing and encoding for LDRB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 2 ++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 16 ++++++++++++++++ test/MC/ARM/basic-thumb-instructions.s | 20 ++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 0c7e349698b..35a745aa78a 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -179,11 +179,13 @@ def t_addrmode_is2 : Operand, // t_addrmode_is1 := reg + imm5 // +def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } def t_addrmode_is1 : Operand, ComplexPattern { let EncoderMethod = "getAddrModeISOpValue"; let DecoderMethod = "DecodeThumbAddrModeIS"; let PrintMethod = "printThumbAddrModeImm5S1Operand"; + let ParserMatchClass = t_addrmode_is1_asm_operand; let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); } diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index b6fce294f2a..d04b9b73cc4 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -628,6 +628,15 @@ public: int64_t Val = Mem.OffsetImm->getValue(); return Val >= 0 && Val <= 124 && (Val % 4) == 0; } + bool isMemThumbRIs1() const { + if (Kind != Memory || Mem.OffsetRegNum != 0 || + !isARMLowRegister(Mem.BaseRegNum)) + return false; + // Immediate offset in range [0, 31]. + if (!Mem.OffsetImm) return true; + int64_t Val = Mem.OffsetImm->getValue(); + return Val >= 0 && Val <= 31; + } bool isMemThumbSPI() const { if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP) return false; @@ -1000,6 +1009,13 @@ public: Inst.addOperand(MCOperand::CreateImm(Val)); } + void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0; + Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); + Inst.addOperand(MCOperand::CreateImm(Val)); + } + void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0; diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s index deedd3be00d..4a45820b88a 100644 --- a/test/MC/ARM/basic-thumb-instructions.s +++ b/test/MC/ARM/basic-thumb-instructions.s @@ -210,3 +210,23 @@ _func: ldr r1, [r2, r3] @ CHECK: ldr r1, [r2, r3] @ encoding: [0xd1,0x58] + + +@------------------------------------------------------------------------------ +@ LDRB (immediate) +@------------------------------------------------------------------------------ + ldrb r4, [r3] + ldrb r5, [r6, #0] + ldrb r6, [r7, #31] + +@ CHECK: ldrb r4, [r3] @ encoding: [0x1c,0x78] +@ CHECK: ldrb r5, [r6] @ encoding: [0x35,0x78] +@ CHECK: ldrb r6, [r7, #31] @ encoding: [0xfe,0x7f] + + +@------------------------------------------------------------------------------ +@ LDRB (register) +@------------------------------------------------------------------------------ + ldrb r6, [r4, r5] + +@ CHECK: ldrb r6, [r4, r5] @ encoding: [0x66,0x5d] -- 2.11.0