From 49b3215d7076db8b9afe8998b01ef250795b5892 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Mon, 26 Oct 2015 18:41:27 -0700 Subject: [PATCH] i965: Combine register file field. The first four values (2-bits) are hardware values, and VGRF, ATTR, and UNIFORM remain values used in the IR. Reviewed-by: Emil Velikov Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_defines.h | 11 +++++++++++ src/mesa/drivers/dri/i965/brw_fs.cpp | 5 ++--- src/mesa/drivers/dri/i965/brw_ir_fs.h | 4 ++-- src/mesa/drivers/dri/i965/brw_ir_vec4.h | 8 ++++---- src/mesa/drivers/dri/i965/brw_reg.h | 4 ++-- src/mesa/drivers/dri/i965/brw_shader.h | 13 ------------- src/mesa/drivers/dri/i965/brw_vec4.cpp | 16 ++++++---------- 7 files changed, 27 insertions(+), 34 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 47350301a14..5044982caec 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1404,6 +1404,17 @@ enum PACKED brw_reg_file { BRW_GENERAL_REGISTER_FILE = 1, BRW_MESSAGE_REGISTER_FILE = 2, BRW_IMMEDIATE_VALUE = 3, + + ARF = BRW_ARCHITECTURE_REGISTER_FILE, + FIXED_GRF = BRW_GENERAL_REGISTER_FILE, + MRF = BRW_MESSAGE_REGISTER_FILE, + IMM = BRW_IMMEDIATE_VALUE, + + /* These are not hardware values */ + VGRF, + ATTR, + UNIFORM, /* prog_data->params[reg] */ + BAD_FILE, }; #define BRW_HW_REG_TYPE_UD 0 diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 9a898726048..b8c88f73dfa 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -424,7 +424,6 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3) fs_reg::fs_reg(struct brw_reg reg) : backend_reg(reg) { - this->file = (enum register_file)reg.file; this->reg_offset = 0; this->subreg_offset = 0; this->reladdr = NULL; @@ -959,7 +958,7 @@ fs_visitor::vgrf(const glsl_type *const type) brw_type_for_base_type(type)); } -fs_reg::fs_reg(enum register_file file, int nr) +fs_reg::fs_reg(enum brw_reg_file file, int nr) { init(); this->file = file; @@ -968,7 +967,7 @@ fs_reg::fs_reg(enum register_file file, int nr) this->stride = (file == UNIFORM ? 0 : 1); } -fs_reg::fs_reg(enum register_file file, int nr, enum brw_reg_type type) +fs_reg::fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type) { init(); this->file = file; diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h index 61e72f7d536..7e977e9e727 100644 --- a/src/mesa/drivers/dri/i965/brw_ir_fs.h +++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h @@ -42,8 +42,8 @@ public: explicit fs_reg(uint8_t vf[4]); explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3); fs_reg(struct brw_reg reg); - fs_reg(enum register_file file, int nr); - fs_reg(enum register_file file, int nr, enum brw_reg_type type); + fs_reg(enum brw_reg_file file, int nr); + fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type); bool equals(const fs_reg &r) const; bool is_contiguous() const; diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h index dcec5f30b06..110e64b979e 100644 --- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h @@ -39,7 +39,7 @@ public: void init(); - src_reg(register_file file, int nr, const glsl_type *type); + src_reg(enum brw_reg_file file, int nr, const glsl_type *type); src_reg(); src_reg(float f); src_reg(uint32_t u); @@ -108,10 +108,10 @@ public: void init(); dst_reg(); - dst_reg(register_file file, int nr); - dst_reg(register_file file, int nr, const glsl_type *type, + dst_reg(enum brw_reg_file file, int nr); + dst_reg(enum brw_reg_file file, int nr, const glsl_type *type, unsigned writemask); - dst_reg(register_file file, int nr, brw_reg_type type, + dst_reg(enum brw_reg_file file, int nr, brw_reg_type type, unsigned writemask); dst_reg(struct brw_reg reg); dst_reg(class vec4_visitor *v, const struct glsl_type *type); diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h index a2f41559503..3da83b43b5d 100644 --- a/src/mesa/drivers/dri/i965/brw_reg.h +++ b/src/mesa/drivers/dri/i965/brw_reg.h @@ -232,11 +232,11 @@ const char *brw_reg_type_letters(unsigned brw_reg_type); */ struct brw_reg { enum brw_reg_type type:4; - enum brw_reg_file file:2; + enum brw_reg_file file:3; /* :2 hardware format */ unsigned negate:1; /* source only */ unsigned abs:1; /* source only */ unsigned address_mode:1; /* relative addressing, hopefully! */ - unsigned pad0:2; + unsigned pad0:1; unsigned subnr:5; /* :1 in align16 */ unsigned nr:16; diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index 767752101ca..c851941021d 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -38,17 +38,6 @@ #define MAX_SAMPLER_MESSAGE_SIZE 11 #define MAX_VGRF_SIZE 16 -enum PACKED register_file { - ARF, - FIXED_GRF, - MRF, - IMM, - VGRF, - ATTR, - UNIFORM, /* prog_data->params[reg] */ - BAD_FILE, -}; - #ifdef __cplusplus struct backend_reg : public brw_reg { @@ -62,8 +51,6 @@ struct backend_reg : public brw_reg bool is_accumulator() const; bool in_range(const backend_reg &r, unsigned n) const; - enum register_file file; /**< Register file: VGRF, MRF, IMM. */ - /** * Offset within the virtual register. * diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 60d4ed90e12..c39e8545c3b 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -51,7 +51,7 @@ src_reg::init() this->file = BAD_FILE; } -src_reg::src_reg(register_file file, int nr, const glsl_type *type) +src_reg::src_reg(enum brw_reg_file file, int nr, const glsl_type *type) { init(); @@ -119,7 +119,6 @@ src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3) src_reg::src_reg(struct brw_reg reg) : backend_reg(reg) { - this->file = (enum register_file)reg.file; this->reg_offset = 0; this->reladdr = NULL; } @@ -127,7 +126,6 @@ src_reg::src_reg(struct brw_reg reg) : src_reg::src_reg(const dst_reg ®) : backend_reg(static_cast(reg)) { - this->file = (enum register_file)reg.file; this->reg_offset = reg.reg_offset; this->reladdr = reg.reladdr; this->swizzle = brw_swizzle_for_mask(reg.writemask); @@ -146,7 +144,7 @@ dst_reg::dst_reg() init(); } -dst_reg::dst_reg(register_file file, int nr) +dst_reg::dst_reg(enum brw_reg_file file, int nr) { init(); @@ -154,18 +152,18 @@ dst_reg::dst_reg(register_file file, int nr) this->nr = nr; } -dst_reg::dst_reg(register_file file, int nr, const glsl_type *type, +dst_reg::dst_reg(enum brw_reg_file file, int nr, const glsl_type *type, unsigned writemask) { init(); - this->file = (enum register_file)file; + this->file = file; this->nr = nr; this->type = brw_type_for_base_type(type); this->writemask = writemask; } -dst_reg::dst_reg(register_file file, int nr, brw_reg_type type, +dst_reg::dst_reg(enum brw_reg_file file, int nr, brw_reg_type type, unsigned writemask) { init(); @@ -179,7 +177,6 @@ dst_reg::dst_reg(register_file file, int nr, brw_reg_type type, dst_reg::dst_reg(struct brw_reg reg) : backend_reg(reg) { - this->file = (enum register_file)reg.file; this->reg_offset = 0; this->reladdr = NULL; } @@ -187,7 +184,6 @@ dst_reg::dst_reg(struct brw_reg reg) : dst_reg::dst_reg(const src_reg ®) : backend_reg(static_cast(reg)) { - this->file = reg.file; this->reg_offset = reg.reg_offset; this->writemask = brw_mask_for_swizzle(reg.swizzle); this->reladdr = reg.reladdr; @@ -345,7 +341,7 @@ vec4_visitor::opt_vector_float() bool progress = false; int last_reg = -1, last_reg_offset = -1; - enum register_file last_reg_file = BAD_FILE; + enum brw_reg_file last_reg_file = BAD_FILE; int remaining_channels = 0; uint8_t imm[4]; -- 2.11.0