From 4a3c57b63a85a1b3db4c141ea6d6edf13830f017 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Thu, 8 Jun 2017 20:56:36 +0000 Subject: [PATCH] [Hexagon] Skip mux generation when predicate register is undefined git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305014 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonGenMux.cpp | 5 ++++- test/CodeGen/Hexagon/mux-undef.ll | 27 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/Hexagon/mux-undef.ll diff --git a/lib/Target/Hexagon/HexagonGenMux.cpp b/lib/Target/Hexagon/HexagonGenMux.cpp index d9adc2b324e..3c37d9ebb0e 100644 --- a/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/lib/Target/Hexagon/HexagonGenMux.cpp @@ -235,8 +235,11 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) { unsigned DR = MI->getOperand(0).getReg(); if (isRegPair(DR)) continue; + MachineOperand &PredOp = MI->getOperand(1); + if (PredOp.isUndef()) + continue; - unsigned PR = MI->getOperand(1).getReg(); + unsigned PR = PredOp.getReg(); unsigned Idx = I2X.lookup(MI); CondsetMap::iterator F = CM.find(DR); bool IfTrue = HII->isPredicatedTrue(Opc); diff --git a/test/CodeGen/Hexagon/mux-undef.ll b/test/CodeGen/Hexagon/mux-undef.ll new file mode 100644 index 00000000000..3780a329b1e --- /dev/null +++ b/test/CodeGen/Hexagon/mux-undef.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; +; Make sure this test compiles successfully. +; CHECK: jumpr r31 + +target triple = "hexagon--elf" + +; Function Attrs: nounwind +define i32 @fred() #0 { +b0: + call void @foo() #0 + br label %b1 + +b1: ; preds = %b0 + br i1 undef, label %b2, label %b3 + +b2: ; preds = %b1 + br label %b3 + +b3: ; preds = %b2, %b1 + %v4 = phi i32 [ 1, %b1 ], [ 2, %b2 ] + ret i32 %v4 +} + +declare void @foo() #0 + +attributes #0 = { nounwind "target-cpu"="hexagonv60" } -- 2.11.0