From 4a5c030b83b62c067b0a3cc94dc4a51fe185e85a Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sat, 20 Aug 2016 23:09:57 +0000
Subject: [PATCH] [X86][SSE] Regenerate 32-bit buildvector test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279389 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/dagcombine-buildvector.ll | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/test/CodeGen/X86/dagcombine-buildvector.ll b/test/CodeGen/X86/dagcombine-buildvector.ll
index 3a6231ade1a..5922b1c810a 100644
--- a/test/CodeGen/X86/dagcombine-buildvector.ll
+++ b/test/CodeGen/X86/dagcombine-buildvector.ll
@@ -1,21 +1,30 @@
-; RUN: llc < %s -march=x86 -mcpu=penryn | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mcpu=penryn | FileCheck %s --check-prefix=CHECK
 
 ; Shows a dag combine bug that will generate an illegal build vector
 ; with v2i64 build_vector i32, i32.
 
-; CHECK-LABEL: test:
-; CHECK: unpcklpd
-; CHECK: movapd
 define void @test(<2 x double>* %dst, <4 x double> %src) nounwind {
+; CHECK-LABEL: test:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT:    movapd %xmm0, (%eax)
+; CHECK-NEXT:    retl
 entry:
-        %tmp7.i = shufflevector <4 x double> %src, <4 x double> undef, <2 x i32> < i32 0, i32 2 >
+        %tmp7.i = shufflevector <4 x double> %src, <4 x double> undef, <2 x i32> <i32 0, i32 2>
         store <2 x double> %tmp7.i, <2 x double>* %dst
         ret void
 }
 
-; CHECK-LABEL: test2:
-; CHECK: movdqa
 define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; CHECK-NEXT:    movdqa %xmm0, (%eax)
+; CHECK-NEXT:    retl
 entry:
         %tmp1 = load <4 x i16>, <4 x i16>* %src
         %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
-- 
2.11.0