From 4b8921d1c7bf17a496933dd1a80077404e14e841 Mon Sep 17 00:00:00 2001
From: Bruno Cardoso Lopes <bruno.cardoso@gmail.com>
Date: Fri, 18 Jun 2010 22:10:11 +0000
Subject: [PATCH] Use the new 'defm' class inheritance in SSE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106327 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86InstrSSE.td | 56 +++++++++++++++++++------------------------
 1 file changed, 24 insertions(+), 32 deletions(-)

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 8ffb8e8cd37..e5e9d59e344 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -672,29 +672,25 @@ let Constraints = "$src1 = $dst" in {
 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
                                  SDNode OpNode, bit Commutable = 0> {
 
-  let Constraints = "", isAsmParserOnly = 1, hasVEX_4VPrefix = 1 in {
+  let Constraints = "", isAsmParserOnly = 1 in {
     // Scalar operation, reg+reg.
-    let Prefix = 12 /* XS */ in
-      defm V#NAME#SS : sse12_fp_scalar<opc,
+    defm V#NAME#SS : sse12_fp_scalar<opc,
         !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                   OpNode, FR32, f32mem>;
+                   OpNode, FR32, f32mem>, XS, VEX_4V;
 
-    let Prefix = 11 /* XD */ in
-      defm V#NAME#SD : sse12_fp_scalar<opc,
+    defm V#NAME#SD : sse12_fp_scalar<opc,
         !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                   OpNode, FR64, f64mem>;
+                   OpNode, FR64, f64mem>, XD, VEX_4V;
   }
 
   let Constraints = "$src1 = $dst" in {
     // Scalar operation, reg+reg.
-    let Prefix = 12 /* XS */ in
-      defm SS : sse12_fp_scalar<opc,
-                      !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
-                      OpNode, FR32, f32mem>;
-    let Prefix = 11 /* XD */ in
-      defm SD : sse12_fp_scalar<opc,
-                      !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
-                      OpNode, FR64, f64mem>;
+    defm SS : sse12_fp_scalar<opc,
+                    !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
+                    OpNode, FR32, f32mem>, XS;
+    defm SD : sse12_fp_scalar<opc,
+                    !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
+                    OpNode, FR64, f64mem>, XD;
   }
 
   // Vector operation, reg+reg.
@@ -857,29 +853,25 @@ let Constraints = "$src1 = $dst" in {
 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
                             SDNode OpNode, bit Commutable = 0> {
 
-  let Constraints = "", isAsmParserOnly = 1, hasVEX_4VPrefix = 1 in {
+  let Constraints = "", isAsmParserOnly = 1 in {
     // Scalar operation, reg+reg.
-    let Prefix = 12 /* XS */ in
-      defm V#NAME#SS : sse12_fp_scalar<opc,
-        !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                   OpNode, FR32, f32mem>;
+    defm V#NAME#SS : sse12_fp_scalar<opc,
+      !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                 OpNode, FR32, f32mem>, XS, VEX_4V;
 
-    let Prefix = 11 /* XD */ in
-      defm V#NAME#SD : sse12_fp_scalar<opc,
-        !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                   OpNode, FR64, f64mem>;
+    defm V#NAME#SD : sse12_fp_scalar<opc,
+      !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                 OpNode, FR64, f64mem>, XD, VEX_4V;
   }
 
   let Constraints = "$src1 = $dst" in {
     // Scalar operation, reg+reg.
-    let Prefix = 12 /* XS */ in
-      defm SS : sse12_fp_scalar<opc,
-                      !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
-                      OpNode, FR32, f32mem>;
-    let Prefix = 11 /* XD */ in
-      defm SD : sse12_fp_scalar<opc,
-                      !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
-                      OpNode, FR64, f64mem>;
+    defm SS : sse12_fp_scalar<opc,
+                    !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
+                    OpNode, FR32, f32mem>, XS;
+    defm SD : sse12_fp_scalar<opc,
+                    !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
+                    OpNode, FR64, f64mem>, XD;
   }
 
   // Vector operation, reg+reg.
-- 
2.11.0