From 4e31e85759a0622b25a63300019d04ff031c95e0 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sat, 25 Sep 2021 16:18:41 +0200 Subject: [PATCH] arm64: dts: qcom: sm6125: Improve indentation of multiline properties Some multiline properties (spread out over multiple lines to keep length in check) were not indented properly, leading to misalignment with the items above. The DT file is still small enough to address this early in the process. Signed-off-by: Marijn Suijten Reviewed-by: Martin Botka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210925141841.407257-1-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 46 ++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 0c1057456597..c2317dd29896 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -326,8 +326,8 @@ tlmm: pinctrl@500000 { compatible = "qcom,sm6125-tlmm"; reg = <0x00500000 0x400000>, - <0x00900000 0x400000>, - <0x00d00000 0x400000>; + <0x00900000 0x400000>, + <0x00d00000 0x400000>; reg-names = "west", "south", "east"; interrupts = ; gpio-controller; @@ -391,12 +391,12 @@ reg-names = "hc", "core"; interrupts = , - ; + ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; clock-names = "iface", "core", "xo"; bus-width = <8>; non-removable; @@ -409,12 +409,12 @@ reg-names = "hc"; interrupts = , - ; + ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; clock-names = "iface", "core", "xo"; pinctrl-0 = <&sdc2_state_on>; @@ -433,11 +433,11 @@ ranges; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; @@ -462,11 +462,11 @@ spmi_bus: spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x01c40000 0x1100>, - <0x01e00000 0x2000000>, - <0x03e00000 0x100000>, - <0x03f00000 0xa0000>, - <0x01c0a000 0x26000>; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; @@ -497,7 +497,7 @@ frame@f121000 { frame-number = <0>; interrupts = , - ; + ; reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; }; @@ -548,7 +548,7 @@ intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0f200000 0x20000>, - <0x0f300000 0x100000>; + <0x0f300000 0x100000>; #interrupt-cells = <3>; interrupt-controller; interrupts = ; @@ -558,9 +558,9 @@ timer { compatible = "arm,armv8-timer"; interrupts = ; + GIC_PPI 2 0xf08 + GIC_PPI 3 0xf08 + GIC_PPI 0 0xf08>; clock-frequency = <19200000>; }; }; -- 2.11.0