From 52d265c4ad0ee3afb1c3d032aa5a2cb6e2bc3f17 Mon Sep 17 00:00:00 2001 From: Changpeng Fang Date: Fri, 11 May 2018 22:17:57 +0000 Subject: [PATCH] AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction. Summary: We have no logic to promote alloca to vector for an AddrSpaceCast instruction. Reviewer: arsenm Differential Revision: https://reviews.llvm.org/D45993 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332147 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp | 1 - test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll | 27 ++++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll diff --git a/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp index 336467af06d..7d28c3c8259 100644 --- a/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp +++ b/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp @@ -328,7 +328,6 @@ static bool canVectorizeInst(Instruction *Inst, User *User) { return isa(LI->getPointerOperand()) && !LI->isVolatile(); } case Instruction::BitCast: - case Instruction::AddrSpaceCast: return true; case Instruction::Store: { // Must be the stored pointer operand, not a stored value, plus diff --git a/test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll b/test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll new file mode 100644 index 00000000000..bd052c27ac0 --- /dev/null +++ b/test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll @@ -0,0 +1,27 @@ +; RUN: opt -S -mtriple=amdgcn-- -data-layout=A5 -amdgpu-promote-alloca -sroa -instcombine < %s | FileCheck -check-prefix=OPT %s + +; Should give up promoting alloca to vector with an addrspacecast. + +; OPT-LABEL: @vector_addrspacecast( +; OPT: alloca [3 x i32] +; OPT: store i32 0, i32 addrspace(5)* %a0, align 4 +; OPT: store i32 1, i32 addrspace(5)* %a1, align 4 +; OPT: store i32 2, i32 addrspace(5)* %a2, align 4 +; OPT: %tmp = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i64 0, i64 %index +; OPT: %ac = addrspacecast i32 addrspace(5)* %tmp to i32* +; OPT: %data = load i32, i32* %ac, align 4 +define amdgpu_kernel void @vector_addrspacecast(i32 addrspace(1)* %out, i64 %index) { +entry: + %alloca = alloca [3 x i32], addrspace(5) + %a0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i32 0, i32 0 + %a1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i32 0, i32 1 + %a2 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i32 0, i32 2 + store i32 0, i32 addrspace(5)* %a0 + store i32 1, i32 addrspace(5)* %a1 + store i32 2, i32 addrspace(5)* %a2 + %tmp = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i64 0, i64 %index + %ac = addrspacecast i32 addrspace(5)* %tmp to i32 * + %data = load i32, i32 * %ac + store i32 %data, i32 addrspace(1)* %out + ret void +} -- 2.11.0