From 53a96f264ef1148873c2c08bededc4c04a17078c Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 14 Mar 2017 04:18:25 +0000 Subject: [PATCH] [AVX-512] Pre-emptively fix more places in fastisel where we might copy a VK1 register into a AH/BH/CH/DH register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297704 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86FastISel.cpp | 37 ++++++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 4eec15779a1..67a1e12f6cd 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -537,6 +537,15 @@ bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, case MVT::f80: // No f80 support yet. default: return false; case MVT::i1: { + // In case ValReg is a K register, COPY to a GPR + if (MRI.getRegClass(ValReg) == &X86::VK1RegClass) { + unsigned KValReg = ValReg; + ValReg = createResultReg(Subtarget->is64Bit() ? &X86::GR8RegClass + : &X86::GR8_ABCD_LRegClass); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, + TII.get(TargetOpcode::COPY), ValReg) + .addReg(KValReg); + } // Mask out all but lowest bit. unsigned AndResult = createResultReg(&X86::GR8RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, @@ -1268,6 +1277,15 @@ bool X86FastISel::X86SelectRet(const Instruction *I) { if (SrcVT == MVT::i1) { if (Outs[0].Flags.isSExt()) return false; + // In case SrcReg is a K register, COPY to a GPR + if (MRI.getRegClass(SrcReg) == &X86::VK1RegClass) { + unsigned KSrcReg = SrcReg; + SrcReg = createResultReg(Subtarget->is64Bit() ? &X86::GR8RegClass + : &X86::GR8_ABCD_LRegClass); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, + TII.get(TargetOpcode::COPY), SrcReg) + .addReg(KSrcReg); + } SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false); SrcVT = MVT::i8; } @@ -1559,15 +1577,14 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) { // Handle zero-extension from i1 to i8, which is common. MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType()); if (SrcVT == MVT::i1) { - if (!Subtarget->is64Bit()) { - // If this isn't a 64-bit target we need to constrain the reg class - // to avoid high registers here otherwise we might use a high register - // to copy from a mask register. - unsigned OldReg = ResultReg; - ResultReg = createResultReg(&X86::GR8_ABCD_LRegClass); + // In case ResultReg is a K register, COPY to a GPR + if (MRI.getRegClass(ResultReg) == &X86::VK1RegClass) { + unsigned KResultReg = ResultReg; + ResultReg = createResultReg(Subtarget->is64Bit() ? &X86::GR8RegClass + : &X86::GR8_ABCD_LRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), ResultReg) - .addReg(OldReg); + .addReg(KResultReg); } // Set the high bits to zero. @@ -2096,7 +2113,8 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { // In case OpReg is a K register, COPY to a GPR if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { unsigned KCondReg = CondReg; - CondReg = createResultReg(&X86::GR8RegClass); + CondReg = createResultReg(Subtarget->is64Bit() ? + &X86::GR8RegClass : &X86::GR8_ABCD_LRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), CondReg) .addReg(KCondReg, getKillRegState(CondIsKill)); @@ -2309,7 +2327,8 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) { // In case OpReg is a K register, COPY to a GPR if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { unsigned KCondReg = CondReg; - CondReg = createResultReg(&X86::GR8RegClass); + CondReg = createResultReg(Subtarget->is64Bit() ? + &X86::GR8RegClass : &X86::GR8_ABCD_LRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), CondReg) .addReg(KCondReg, getKillRegState(CondIsKill)); -- 2.11.0