From 54117b90ffd8a3977917971c3bd99bb5242710d9 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 24 Feb 2020 17:28:44 +0000 Subject: [PATCH] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We missed an instance of using FIELD_EX32 on a 64-bit ID register, in isar_feature_aa64_pmu_8_4(). Fix it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20200224172846.13053-2-peter.maydell@linaro.org --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05aa9711cd..6013287f62 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3770,8 +3770,8 @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) { - return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && - FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } /* -- 2.11.0