From 593a05ca1e177fc584cba399bf66fbf437ba75d9 Mon Sep 17 00:00:00 2001
From: Petar Jovanovic <petar.jovanovic@imgtec.com>
Date: Sun, 10 Aug 2014 22:49:54 +0000
Subject: [PATCH] Add support for scalarizing cttz_zero_undef

Follow up to r214266. Add missing case in ScalarizeVectorResult() for
cttz_zero_undef.

Differential Revision: http://reviews.llvm.org/D4813

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215330 91177308-0d34-0410-b5e6-96231b3b80d8

(cherry picked from commit cddb0cfe383207ccec0cc797db401854e5f0c672)

Change-Id: I998526c9a9a77cb340c92ad6b292e7e5a9ba5767
---
 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp |  1 +
 test/CodeGen/Mips/cttz-v.ll                      | 37 ++++++++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 test/CodeGen/Mips/cttz-v.ll

diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index dd98ffd6f8b..71240fc60cd 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -72,6 +72,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::CTLZ_ZERO_UNDEF:
   case ISD::CTPOP:
   case ISD::CTTZ:
+  case ISD::CTTZ_ZERO_UNDEF:
   case ISD::FABS:
   case ISD::FCEIL:
   case ISD::FCOS:
diff --git a/test/CodeGen/Mips/cttz-v.ll b/test/CodeGen/Mips/cttz-v.ll
new file mode 100644
index 00000000000..9470441da90
--- /dev/null
+++ b/test/CodeGen/Mips/cttz-v.ll
@@ -0,0 +1,37 @@
+; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
+
+declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1)
+
+define <2 x i32> @cttzv2i32(<2 x i32> %x) {
+entry:
+; MIPS32-DAG: addiu   $[[R0:[0-9]+]], $4, -1
+; MIPS32-DAG: not     $[[R1:[0-9]+]], $4
+; MIPS32-DAG: and     $[[R2:[0-9]+]], $[[R1]], $[[R0]]
+; MIPS32-DAG: clz     $[[R3:[0-9]+]], $[[R2]]
+; MIPS32-DAG: addiu   $[[R4:[0-9]+]], $zero, 32
+; MIPS32-DAG: subu    $2, $[[R4]], $[[R3]]
+; MIPS32-DAG: addiu   $[[R5:[0-9]+]], $5, -1
+; MIPS32-DAG: not     $[[R6:[0-9]+]], $5
+; MIPS32-DAG: and     $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MIPS32-DAG: clz     $[[R8:[0-9]+]], $[[R7]]
+; MIPS32-DAG: jr      $ra
+; MIPS32-DAG: subu    $3, $[[R4]], $[[R8]]
+
+; MIPS64-DAG: addiu   $[[R0:[0-9]+]], $4, -1
+; MIPS64-DAG: not     $[[R1:[0-9]+]], $4
+; MIPS64-DAG: and     $[[R2:[0-9]+]], $[[R1]], $[[R0]]
+; MIPS64-DAG: clz     $[[R3:[0-9]+]], $[[R2]]
+; MIPS64-DAG: addiu   $[[R4:[0-9]+]], $zero, 32
+; MIPS64-DAG: subu    $2, $[[R4]], $[[R3]]
+; MIPS64-DAG: addiu   $[[R5:[0-9]+]], $5, -1
+; MIPS64-DAG: not     $[[R6:[0-9]+]], $5
+; MIPS64-DAG: and     $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MIPS64-DAG: clz     $[[R8:[0-9]+]], $[[R7]]
+; MIPS64-DAG: jr      $ra
+; MIPS64-DAG: subu    $3, $[[R4]], $[[R8]]
+
+  %ret = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %x, i1 true)
+  ret <2 x i32> %ret
+}
+
-- 
2.11.0