From 59758c433797035170ceef7008c0d5b117dc59c0 Mon Sep 17 00:00:00 2001 From: Tilmann Scheller Date: Fri, 29 Aug 2014 17:19:00 +0000 Subject: [PATCH] [ARM] Add Thumb-2 code size optimization test for ASR (register). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216746 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/thumb2-size-opt.ll | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/test/CodeGen/ARM/thumb2-size-opt.ll b/test/CodeGen/ARM/thumb2-size-opt.ll index bc7e6ef9e1a..e201cd5159f 100644 --- a/test/CodeGen/ARM/thumb2-size-opt.ll +++ b/test/CodeGen/ARM/thumb2-size-opt.ll @@ -18,3 +18,12 @@ entry: %shr = ashr i32 %a, 13 ret i32 %shr } + +define i32 @asr-reg(i32 %a, i32 %b) nounwind readnone { +; CHECK-LABEL: "asr-reg": +; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}] +; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}] +entry: + %shr = ashr i32 %a, %b + ret i32 %shr +} -- 2.11.0