From 5a5039a2378cad9db24fb709e44781c4a74bd054 Mon Sep 17 00:00:00 2001
From: Matthias Braun <matze@braunis.de>
Date: Fri, 16 Dec 2016 23:55:43 +0000
Subject: [PATCH] AArch64: Enable post-ra liveness updates

Differential Revision: https://reviews.llvm.org/D27559

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290014 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp  |  7 ++++++-
 lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp |  3 +++
 lib/Target/AArch64/AArch64RegisterInfo.h         |  4 ++++
 test/CodeGen/AArch64/ldst-opt-dbg-limit.mir      | 10 +++++-----
 test/CodeGen/AArch64/movimm-wzr.mir              |  2 +-
 5 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 94b208a8e7d..fe1c0beee0e 100644
--- a/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -897,9 +897,14 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
   case AArch64::MOVi64imm:
     return expandMOVImm(MBB, MBBI, 64);
   case AArch64::RET_ReallyLR: {
+    // Hiding the LR use with RET_ReallyLR may lead to extra kills in the
+    // function and missing live-ins. We are fine in practice because callee
+    // saved register handling ensures the register value is restored before
+    // RET, but we need the undef flag here to appease the MachineVerifier
+    // liveness checks.
     MachineInstrBuilder MIB =
         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
-          .addReg(AArch64::LR);
+          .addReg(AArch64::LR, RegState::Undef);
     transferImpOps(MI, MIB, MIB);
     MI.eraseFromParent();
     return true;
diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 6e157638184..dcb05601e5f 100644
--- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -767,6 +767,7 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
     // Remove the load, if the destination register of the loads is the same
     // register for stored value.
     if (StRt == LdRt && LoadSize == 8) {
+      StoreI->clearRegisterKills(StRt, TRI);
       DEBUG(dbgs() << "Remove load instruction:\n    ");
       DEBUG(LoadI->print(dbgs()));
       DEBUG(dbgs() << "\n");
@@ -831,6 +832,8 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
               .addImm(Imms);
     }
   }
+  StoreI->clearRegisterKills(StRt, TRI);
+
   (void)BitExtMI;
 
   DEBUG(dbgs() << "Promoting load by replacing :\n    ");
diff --git a/lib/Target/AArch64/AArch64RegisterInfo.h b/lib/Target/AArch64/AArch64RegisterInfo.h
index 098657fe883..8ce893516fe 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.h
+++ b/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -95,6 +95,10 @@ public:
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
                                MachineFunction &MF) const override;
+
+  bool trackLivenessAfterRegAlloc(const MachineFunction&) const override {
+    return true;
+  }
 };
 
 } // end namespace llvm
diff --git a/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir b/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
index 88a4b2c0cd9..45542cae98f 100644
--- a/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
+++ b/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
@@ -28,7 +28,7 @@
 name:            promote-load-from-store
 alignment:       2
 exposesReturnsTwice: false
-tracksRegLiveness: false
+tracksRegLiveness: true
 liveins:         
   - { reg: '%x0' }
   - { reg: '%w1' }
@@ -48,7 +48,7 @@ frameInfo:
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0 (%ir-block.0):
-    liveins: %w1, %x0
+    liveins: %w1, %x0, %lr
   
     STRWui killed %w1, %x0, 0 :: (store 4 into %ir.dst)
     CFI_INSTRUCTION 0
@@ -76,13 +76,13 @@ body:             |
 
 ...
 # CHECK-LABEL: name:            promote-load-from-store
-# CHECK: STRWui killed %w1
+# CHECK: STRWui %w1
 # CHECK: UBFMWri %w1
 ---
 name:            store-pair
 alignment:       2
 exposesReturnsTwice: false
-tracksRegLiveness: false
+tracksRegLiveness: true
 liveins:         
   - { reg: '%x0' }
   - { reg: '%w1' }
@@ -102,7 +102,7 @@ frameInfo:
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0 (%ir-block.0):
-    liveins: %w1, %x0
+    liveins: %w1, %x0, %lr
   
     STRWui %w1, %x0, 0 :: (store 4 into %ir.dst01)
     CFI_INSTRUCTION 0
diff --git a/test/CodeGen/AArch64/movimm-wzr.mir b/test/CodeGen/AArch64/movimm-wzr.mir
index c6bfcf121a3..093f85bd931 100644
--- a/test/CodeGen/AArch64/movimm-wzr.mir
+++ b/test/CodeGen/AArch64/movimm-wzr.mir
@@ -39,4 +39,4 @@ body:             |
 ...
 
 # CHECK: bb.0
-# CHECK-NEXT: RET %lr
+# CHECK-NEXT: RET undef %lr
-- 
2.11.0