From 5c064efe8a24d872012c8cbe0db90d5e50ee5c14 Mon Sep 17 00:00:00 2001 From: fche Date: Mon, 7 May 2001 17:55:20 +0000 Subject: [PATCH] * cgen asm/disasm [opcodes/ChangeLog] 2001-05-07 Frank Ch. Eigler * cgen-dis.in (default_print_insn): Tolerate min * iformat.scm (compute-insn-base-mask-length): Rewrite to tolerate various-base-length instruction sets. --- cgen/ChangeLog | 5 +++++ cgen/iformat.scm | 18 +++++++++++++++--- opcodes/ChangeLog | 7 +++++++ opcodes/cgen-dis.in | 15 ++++++++++++--- opcodes/cgen-ibld.in | 4 ++-- 5 files changed, 41 insertions(+), 8 deletions(-) diff --git a/cgen/ChangeLog b/cgen/ChangeLog index 16f2d5b7bb..13a02223da 100644 --- a/cgen/ChangeLog +++ b/cgen/ChangeLog @@ -1,3 +1,8 @@ +2001-05-07 Frank Ch. Eigler + + * iformat.scm (compute-insn-base-mask-length): Rewrite to tolerate + various-base-length instruction sets. + 2001-04-02 Ben Elliston * sid-cpu.scm (-last-insn): New function. diff --git a/cgen/iformat.scm b/cgen/iformat.scm index 5ddef2536d..9a54d56c4b 100644 --- a/cgen/iformat.scm +++ b/cgen/iformat.scm @@ -90,11 +90,23 @@ ) ; Given FLD-LIST, compute the base length in bits. -; Computing the min of state-base-insn-bitsize and the total-length -; is for [V]LIW instruction sets. +; +; For variable length instruction sets, or with cpus with multiple +; instruction sets, compute the base appropriate for this set of +; ifields. Check that ifields are not shared among isas with +; inconsistent base insn lengths. (define (compute-insn-base-mask-length fld-list) - (min (state-base-insn-bitsize) (compute-insn-length fld-list)) + (let* ((isa-base-bitsizes + (remove-duplicates + (map isa-base-insn-bitsize + (map current-isa-lookup + (collect (lambda (ifld) + (bitset-attr->list (atlist-attr-value (obj-atlist ifld) 'ISA #f))) + fld-list)))))) + (if (= 1 (length isa-base-bitsizes)) + (min (car isa-base-bitsizes) (compute-insn-length fld-list)) + (error "ifields have inconsistent isa/base-insn-size values:" isa-base-bitsizes))) ) ; Given FLD-LIST, compute the bitmask of constant values in the base part diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f4247e96c6..d39051533a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2001-05-07 Frank Ch. Eigler + + * cgen-dis.in (default_print_insn): Tolerate min * disassemble.c (disassembler_usage): Remove unused attribute. diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index b2865f8cba..91fed7b0a7 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -334,18 +334,27 @@ default_print_insn (cd, pc, info) disassemble_info *info; { char buf[CGEN_MAX_INSN_SIZE]; + int buflen; int status; - /* Read the base part of the insn. */ + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } - status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } - return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8); + return print_insn (cd, pc, info, buf, buflen); } /* Main entry point. diff --git a/opcodes/cgen-ibld.in b/opcodes/cgen-ibld.in index 528e60979c..ca2f1e5fcc 100644 --- a/opcodes/cgen-ibld.in +++ b/opcodes/cgen-ibld.in @@ -428,9 +428,9 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, word_length = total_length; } - /* Does the value reside in INSN_VALUE? */ + /* Does the value reside in INSN_VALUE, and at the right alignment? */ - if (CGEN_INT_INSN_P || word_offset == 0) + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) { if (CGEN_INSN_LSB0_P) value = insn_value >> ((word_offset + start + 1) - length); -- 2.11.0