From 5de49bd50b104d4de97f9856a7a75d07276f9867 Mon Sep 17 00:00:00 2001 From: astoria-d Date: Fri, 9 Jan 2015 20:44:34 +0900 Subject: [PATCH] ppu vga working --- tools/qt_proj_test5/ppu.vhd | 16 +++-- tools/qt_proj_test5/qt_proj_test5.vhd | 45 +++++++++++-- tools/qt_proj_test5/render.vhd | 11 ++-- .../modelsim/qt_proj_test5_run_msim_gate_vhdl.do | 1 + tools/qt_proj_test5/vga.vhd | 74 ++++++++++++---------- 5 files changed, 100 insertions(+), 47 deletions(-) diff --git a/tools/qt_proj_test5/ppu.vhd b/tools/qt_proj_test5/ppu.vhd index 18db12f..89cfc57 100644 --- a/tools/qt_proj_test5/ppu.vhd +++ b/tools/qt_proj_test5/ppu.vhd @@ -12,10 +12,12 @@ entity ppu is signal dbg_ppu_clk : out std_logic; signal dbg_nes_x : out std_logic_vector (8 downto 0); signal dbg_vga_x : out std_logic_vector (9 downto 0); - signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); - signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); - signal dbg_ppu_addr_we_n : out std_logic; - signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0); + signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); + signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_plt_addr : out std_logic_vector (4 downto 0); + + signal dbg_ppu_addr_we_n : out std_logic; + signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0); clk : in std_logic; @@ -50,8 +52,9 @@ component ppu_render signal dbg_ppu_clk : out std_logic; signal dbg_nes_x : out std_logic_vector (8 downto 0); signal dbg_vga_x : out std_logic_vector (9 downto 0); - signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); - signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); + signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_plt_addr : out std_logic_vector (4 downto 0); clk : in std_logic; @@ -196,6 +199,7 @@ begin dbg_nes_x , dbg_vga_x , dbg_disp_nt, dbg_disp_attr, dbg_disp_ptn_h, dbg_disp_ptn_l, + dbg_plt_addr , clk, vga_clk, mem_clk, rst_n, rd_n, wr_n, ale, vram_ad, vram_a, diff --git a/tools/qt_proj_test5/qt_proj_test5.vhd b/tools/qt_proj_test5/qt_proj_test5.vhd index d386c72..7a5a5ee 100644 --- a/tools/qt_proj_test5/qt_proj_test5.vhd +++ b/tools/qt_proj_test5/qt_proj_test5.vhd @@ -21,6 +21,7 @@ entity qt_proj_test5 is signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0); signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_ppu_addr_we_n : out std_logic; signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0); @@ -69,10 +70,12 @@ architecture rtl of qt_proj_test5 is signal dbg_ppu_clk : out std_logic; signal dbg_nes_x : out std_logic_vector (8 downto 0); signal dbg_vga_x : out std_logic_vector (9 downto 0); - signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); - signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); - signal dbg_ppu_addr_we_n : out std_logic; - signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0); + signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); + signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_plt_addr : out std_logic_vector (4 downto 0); + + signal dbg_ppu_addr_we_n : out std_logic; + signal dbg_ppu_clk_cnt : out std_logic_vector(1 downto 0); clk : in std_logic; mem_clk : in std_logic; @@ -172,6 +175,7 @@ architecture rtl of qt_proj_test5 is signal dbg_ppu_addr_dummy : std_logic_vector (13 downto 0); signal dbg_nes_x : std_logic_vector (8 downto 0); signal dbg_vga_x : std_logic_vector (9 downto 0); + signal dbg_plt_addr : std_logic_vector (4 downto 0); begin --ppu/cpu clock generator @@ -181,6 +185,7 @@ begin dbg_cpu_clk <= vga_clk; dbg_ppu_addr <= "00000" & dbg_nes_x; dbg_addr <= "000000" & dbg_vga_x; + dbg_d_io <= "000" & dbg_plt_addr; ppu_inst: ppu port map ( dbg_ppu_ce_n , dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status , @@ -192,6 +197,7 @@ begin dbg_vga_x , dbg_disp_nt, dbg_disp_attr , dbg_disp_ptn_h, dbg_disp_ptn_l , + dbg_plt_addr , dbg_ppu_addr_we_n , dbg_ppu_clk_cnt , @@ -316,6 +322,7 @@ end; ppu_set(16#2006#, 16#3f#); elsif (plt_step_cnt = 2) then ppu_set(16#2006#, 16#00#); + elsif (plt_step_cnt = 4) then --set palette data ppu_set(16#2007#, 16#0f#); @@ -325,9 +332,37 @@ end; ppu_set(16#2007#, 16#10#); elsif (plt_step_cnt = 10) then ppu_set(16#2007#, 16#20#); + + elsif (plt_step_cnt = 12) then + ppu_set(16#2007#, 16#0f#); + elsif (plt_step_cnt = 14) then + ppu_set(16#2007#, 16#04#); + elsif (plt_step_cnt = 16) then + ppu_set(16#2007#, 16#14#); + elsif (plt_step_cnt = 18) then + ppu_set(16#2007#, 16#24#); + + elsif (plt_step_cnt = 20) then + ppu_set(16#2007#, 16#0f#); + elsif (plt_step_cnt = 22) then + ppu_set(16#2007#, 16#08#); + elsif (plt_step_cnt = 24) then + ppu_set(16#2007#, 16#18#); + elsif (plt_step_cnt = 26) then + ppu_set(16#2007#, 16#28#); + + elsif (plt_step_cnt = 28) then + ppu_set(16#2007#, 16#0f#); + elsif (plt_step_cnt = 30) then + ppu_set(16#2007#, 16#0c#); + elsif (plt_step_cnt = 32) then + ppu_set(16#2007#, 16#1c#); + elsif (plt_step_cnt = 34) then + ppu_set(16#2007#, 16#2c#); + else ppu_clr; - if (plt_step_cnt > 10) then + if (plt_step_cnt > 34) then global_step_cnt := global_step_cnt + 1; end if; end if; diff --git a/tools/qt_proj_test5/render.vhd b/tools/qt_proj_test5/render.vhd index 088858f..3322c42 100644 --- a/tools/qt_proj_test5/render.vhd +++ b/tools/qt_proj_test5/render.vhd @@ -8,8 +8,9 @@ entity ppu_render is signal dbg_ppu_clk : out std_logic; signal dbg_nes_x : out std_logic_vector (8 downto 0); signal dbg_vga_x : out std_logic_vector (9 downto 0); - signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); - signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); + signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_plt_addr : out std_logic_vector (4 downto 0); clk : in std_logic; vga_clk : in std_logic; @@ -68,8 +69,9 @@ component vga_ctl signal dbg_ppu_clk : out std_logic; signal dbg_nes_x : out std_logic_vector (8 downto 0); signal dbg_vga_x : out std_logic_vector (9 downto 0); - signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); - signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); + signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_plt_addr : out std_logic_vector (4 downto 0); vga_clk : in std_logic; mem_clk : in std_logic; @@ -149,6 +151,7 @@ begin dbg_vga_x , dbg_disp_nt, dbg_disp_attr , dbg_disp_ptn_h, dbg_disp_ptn_l , + dbg_plt_addr , vga_clk , mem_clk , rst_n , diff --git a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do index 7773d83..8007de6 100644 --- a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do +++ b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do @@ -31,6 +31,7 @@ add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_nt add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_attr add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_h add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_l +add wave -radix hex -label plt_addr sim:/testbench_qt_proj_test5/sim_board/dbg_d_io add wave -divider vga_out diff --git a/tools/qt_proj_test5/vga.vhd b/tools/qt_proj_test5/vga.vhd index 6da3176..5432539 100644 --- a/tools/qt_proj_test5/vga.vhd +++ b/tools/qt_proj_test5/vga.vhd @@ -16,8 +16,9 @@ entity vga_ctl is signal dbg_ppu_clk : out std_logic; signal dbg_nes_x : out std_logic_vector (8 downto 0); signal dbg_vga_x : out std_logic_vector (9 downto 0); - signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); - signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); + signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_plt_addr : out std_logic_vector (4 downto 0); vga_clk : in std_logic; mem_clk : in std_logic; @@ -68,6 +69,7 @@ component ppu_vga_render signal dbg_nes_x : out std_logic_vector (8 downto 0); signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_plt_addr : out std_logic_vector (4 downto 0); clk : in std_logic; mem_clk : in std_logic; @@ -134,6 +136,9 @@ signal oam_plt_addr : std_logic_vector (7 downto 0); signal oam_plt_data : std_logic_vector (7 downto 0); signal v_bus_busy_n : std_logic; signal ppu_status : std_logic_vector (7 downto 0); +signal rr : std_logic_vector (3 downto 0); +signal gg : std_logic_vector (3 downto 0); +signal bb : std_logic_vector (3 downto 0); ---DE1 base clock 50 MHz ---motones sim project uses following clock. @@ -159,11 +164,9 @@ begin v_sync_n <= '0'; x_res_n <= '0'; y_res_n <= '0'; --- --- r<=(others => '0'); --- g<=(others => '0'); --- b<=(others => '0'); --- + bb <= (others => '0'); + gg <= (others => '0'); + rr <= (others => '0'); elsif (rising_edge(vga_clk)) then --xmax = 799 if (vga_x = conv_std_logic_vector(VGA_W_MAX, 10)) then @@ -195,23 +198,17 @@ begin else v_sync_n <= '1'; end if; --- --- if (vga_y <=conv_std_logic_vector((VGA_H) , 10)) then --- if (vga_x < conv_std_logic_vector((VGA_W) , 10)) then --- r<= "0100"; --- g<= "0000"; --- b<= "0010"; --- else --- r<=(others => '0'); --- g<=(others => '0'); --- b<=(others => '0'); --- end if; --- else --- r<=(others => '0'); --- g<=(others => '0'); --- b<=(others => '0'); --- end if; --- + + if (vga_x <= conv_std_logic_vector((VGA_W) , 10) and + vga_y <= conv_std_logic_vector((VGA_H) , 10)) then + bb <= "0110"; + gg <= (others => '1'); + rr <= (others => '0'); + else + bb <= (others => '0'); + gg <= (others => '0'); + rr <= (others => '0'); + end if; end if; end process; @@ -244,7 +241,12 @@ begin end process; --vga emulated render instance... - oam_plt_data <= (others => 'Z'); + r_nw <= '1'; + oam_bus_ce_n <= '1'; + plt_bus_ce_n <= '1'; + oam_plt_addr <= (others => '0'); + oam_plt_data <= (others => 'Z'); + emu_ppu_clk_n <= not emu_ppu_clk; vga_render_inst : ppu_vga_render port map ( @@ -252,6 +254,7 @@ begin dbg_nes_x , dbg_disp_nt, dbg_disp_attr , dbg_disp_ptn_h, dbg_disp_ptn_l , + dbg_plt_addr , emu_ppu_clk_n , mem_clk , @@ -302,6 +305,7 @@ entity ppu_vga_render is signal dbg_nes_x : out std_logic_vector (8 downto 0); signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0); signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0); + signal dbg_plt_addr : out std_logic_vector (4 downto 0); clk : in std_logic; mem_clk : in std_logic; @@ -642,6 +646,7 @@ begin dbg_disp_attr <= disp_attr; dbg_disp_ptn_h <= disp_ptn_h; dbg_disp_ptn_l <= disp_ptn_l; + dbg_plt_addr <= plt_addr; clk_n <= not clk; @@ -981,10 +986,15 @@ begin b <= nes_color_palette(pl_index) (11 downto 8); g <= nes_color_palette(pl_index) (7 downto 4); r <= nes_color_palette(pl_index) (3 downto 0); --- d_print("rgb:" & --- conv_hex8(nes_color_palette(pl_index) (11 downto 8)) & --- conv_hex8(nes_color_palette(pl_index) (7 downto 4)) & --- conv_hex8(nes_color_palette(pl_index) (3 downto 0))); +-- b <= nes_color_palette(1) (11 downto 8); +-- g <= nes_color_palette(2) (7 downto 4); +-- r <= nes_color_palette(3) (3 downto 0); +end; +procedure stop_rgb is +begin + b <= (others => '0'); + g <= (others => '0'); + r <= (others => '0'); end; begin @@ -993,9 +1003,7 @@ end; ppu_status <= (others => '0'); - b <= (others => '0'); - g <= (others => '0'); - r <= (others => '0'); + stop_rgb; else if (clk'event and clk = '0') then d_print("-"); @@ -1296,6 +1304,8 @@ end; (cur_y < conv_std_logic_vector(VSCAN, X_SIZE))) then --output image. output_rgb; + else + stop_rgb; end if; --flag operation -- 2.11.0