From 5e437d3ccdccfd85f6e69ca60f921be2dab62c3c Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Tue, 23 Feb 2021 14:59:32 +0800 Subject: [PATCH] target/riscv: fix vs() to return proper error code vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature is not enabled. If -1 is returned, exception will be raised and cs->exception_index will be set to the negative return value. The exception will then be treated as an instruction access fault instead of illegal instruction fault. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210223065935.20208-1-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fd2e6363f3..d2ae73e4a0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -54,7 +54,7 @@ static int vs(CPURISCVState *env, int csrno) if (env->misa & RVV) { return 0; } - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } static int ctr(CPURISCVState *env, int csrno) -- 2.11.0