From 5f37fd8e2980818ab71bc4b4e21129e29acd73f7 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 24 Jun 2015 14:01:10 +0200 Subject: [PATCH] target-tricore: fix depositing bits from PCXI into ICR Spotted by Coverity, because (env->PCXI & MASK_PCXI_PCPN) >> 24 is always zero. The immediately preceding assignment is also wrong though. Signed-off-by: Paolo Bonzini Signed-off-by: Bastian Koppelmann Message-Id: <1435147270-1040-1-git-send-email-pbonzini@redhat.com> --- target-tricore/op_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c index 10ed541dfd..53edbdae18 100644 --- a/target-tricore/op_helper.c +++ b/target-tricore/op_helper.c @@ -2545,10 +2545,10 @@ void helper_rfm(CPUTriCoreState *env) env->PC = (env->gpr_a[11] & ~0x1); /* ICR.IE = PCXI.PIE; */ env->ICR = (env->ICR & ~MASK_ICR_IE) | - ((env->PCXI & ~MASK_PCXI_PIE) >> 15); + ((env->PCXI & MASK_PCXI_PIE) >> 15); /* ICR.CCPN = PCXI.PCPN; */ env->ICR = (env->ICR & ~MASK_ICR_CCPN) | - ((env->PCXI & ~MASK_PCXI_PCPN) >> 24); + ((env->PCXI & MASK_PCXI_PCPN) >> 24); /* {PCXI, PSW, A[10], A[11]} = M(DCX, 4 * word); */ env->PCXI = cpu_ldl_data(env, env->DCX); psw_write(env, cpu_ldl_data(env, env->DCX+4)); -- 2.11.0