From 6121ddcb93a06421ac5bc54652233dc198d48cc1 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Tue, 19 Feb 2019 13:47:19 +0000 Subject: [PATCH] [RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354323 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../RISCV/calling-conv-ilp32-ilp32f-common.ll | 281 ++++++++++++++++ ... => calling-conv-ilp32-ilp32f-ilp32d-common.ll} | 371 +++++++++------------ test/CodeGen/RISCV/calling-conv-ilp32.ll | 194 +++++++++++ 3 files changed, 633 insertions(+), 213 deletions(-) create mode 100644 test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll rename test/CodeGen/RISCV/{calling-conv.ll => calling-conv-ilp32-ilp32f-ilp32d-common.ll} (90%) create mode 100644 test/CodeGen/RISCV/calling-conv-ilp32.ll diff --git a/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll new file mode 100644 index 00000000000..5c1248aa5fd --- /dev/null +++ b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll @@ -0,0 +1,281 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ +; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s + +; This file contains tests that should have identical output for the ilp32, +; and ilp32f. As well as calling convention details, we check that +; ra and fp are consistently stored to fp-4 and fp-8. + +; Check that on RV32 ilp32[f], double is passed in a pair of registers. Unlike +; the convention for varargs, this need not be an aligned pair. + +define i32 @callee_double_in_regs(i32 %a, double %b) nounwind { +; RV32I-FPELIM-LABEL: callee_double_in_regs: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi sp, sp, -16 +; RV32I-FPELIM-NEXT: sw ra, 12(sp) +; RV32I-FPELIM-NEXT: sw s1, 8(sp) +; RV32I-FPELIM-NEXT: mv s1, a0 +; RV32I-FPELIM-NEXT: mv a0, a1 +; RV32I-FPELIM-NEXT: mv a1, a2 +; RV32I-FPELIM-NEXT: call __fixdfsi +; RV32I-FPELIM-NEXT: add a0, s1, a0 +; RV32I-FPELIM-NEXT: lw s1, 8(sp) +; RV32I-FPELIM-NEXT: lw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi sp, sp, 16 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: callee_double_in_regs: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: sw s1, 4(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: mv s1, a0 +; RV32I-WITHFP-NEXT: mv a0, a1 +; RV32I-WITHFP-NEXT: mv a1, a2 +; RV32I-WITHFP-NEXT: call __fixdfsi +; RV32I-WITHFP-NEXT: add a0, s1, a0 +; RV32I-WITHFP-NEXT: lw s1, 4(sp) +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %b_fptosi = fptosi double %b to i32 + %1 = add i32 %a, %b_fptosi + ret i32 %1 +} + +define i32 @caller_double_in_regs() nounwind { +; RV32I-FPELIM-LABEL: caller_double_in_regs: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi sp, sp, -16 +; RV32I-FPELIM-NEXT: sw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 1 +; RV32I-FPELIM-NEXT: mv a1, zero +; RV32I-FPELIM-NEXT: lui a2, 262144 +; RV32I-FPELIM-NEXT: call callee_double_in_regs +; RV32I-FPELIM-NEXT: lw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi sp, sp, 16 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: caller_double_in_regs: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: addi a0, zero, 1 +; RV32I-WITHFP-NEXT: mv a1, zero +; RV32I-WITHFP-NEXT: lui a2, 262144 +; RV32I-WITHFP-NEXT: call callee_double_in_regs +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %1 = call i32 @callee_double_in_regs(i32 1, double 2.0) + ret i32 %1 +} + +; Check 2x*xlen values are aligned appropriately when passed on the stack +; Must keep define on a single line due to an update_llc_test_checks.py limitation +define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, double %i, i32 %j, [2 x i32] %k) nounwind { +; The double should be 8-byte aligned on the stack, but the two-element array +; should only be 4-byte aligned +; RV32I-FPELIM-LABEL: callee_aligned_stack: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: lw a0, 0(a2) +; RV32I-FPELIM-NEXT: add a0, a0, a7 +; RV32I-FPELIM-NEXT: lw a1, 0(sp) +; RV32I-FPELIM-NEXT: add a0, a0, a1 +; RV32I-FPELIM-NEXT: lw a1, 8(sp) +; RV32I-FPELIM-NEXT: add a0, a0, a1 +; RV32I-FPELIM-NEXT: lw a1, 16(sp) +; RV32I-FPELIM-NEXT: add a0, a0, a1 +; RV32I-FPELIM-NEXT: lw a1, 20(sp) +; RV32I-FPELIM-NEXT: add a0, a0, a1 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: callee_aligned_stack: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: lw a0, 0(a2) +; RV32I-WITHFP-NEXT: add a0, a0, a7 +; RV32I-WITHFP-NEXT: lw a1, 0(s0) +; RV32I-WITHFP-NEXT: add a0, a0, a1 +; RV32I-WITHFP-NEXT: lw a1, 8(s0) +; RV32I-WITHFP-NEXT: add a0, a0, a1 +; RV32I-WITHFP-NEXT: lw a1, 16(s0) +; RV32I-WITHFP-NEXT: add a0, a0, a1 +; RV32I-WITHFP-NEXT: lw a1, 20(s0) +; RV32I-WITHFP-NEXT: add a0, a0, a1 +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %1 = bitcast fp128 %c to i128 + %2 = trunc i128 %1 to i32 + %3 = add i32 %2, %g + %4 = add i32 %3, %h + %5 = bitcast double %i to i64 + %6 = trunc i64 %5 to i32 + %7 = add i32 %4, %6 + %8 = add i32 %7, %j + %9 = extractvalue [2 x i32] %k, 0 + %10 = add i32 %8, %9 + ret i32 %10 +} + +define void @caller_aligned_stack() nounwind { +; The double should be 8-byte aligned on the stack, but the two-element array +; should only be 4-byte aligned +; RV32I-FPELIM-LABEL: caller_aligned_stack: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi sp, sp, -64 +; RV32I-FPELIM-NEXT: sw ra, 60(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 18 +; RV32I-FPELIM-NEXT: sw a0, 24(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 17 +; RV32I-FPELIM-NEXT: sw a0, 20(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 16 +; RV32I-FPELIM-NEXT: sw a0, 16(sp) +; RV32I-FPELIM-NEXT: lui a0, 262236 +; RV32I-FPELIM-NEXT: addi a0, a0, 655 +; RV32I-FPELIM-NEXT: sw a0, 12(sp) +; RV32I-FPELIM-NEXT: lui a0, 377487 +; RV32I-FPELIM-NEXT: addi a0, a0, 1475 +; RV32I-FPELIM-NEXT: sw a0, 8(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 15 +; RV32I-FPELIM-NEXT: sw a0, 0(sp) +; RV32I-FPELIM-NEXT: lui a0, 262153 +; RV32I-FPELIM-NEXT: addi a0, a0, 491 +; RV32I-FPELIM-NEXT: sw a0, 44(sp) +; RV32I-FPELIM-NEXT: lui a0, 545260 +; RV32I-FPELIM-NEXT: addi a0, a0, -1967 +; RV32I-FPELIM-NEXT: sw a0, 40(sp) +; RV32I-FPELIM-NEXT: lui a0, 964690 +; RV32I-FPELIM-NEXT: addi a0, a0, -328 +; RV32I-FPELIM-NEXT: sw a0, 36(sp) +; RV32I-FPELIM-NEXT: lui a0, 335544 +; RV32I-FPELIM-NEXT: addi a0, a0, 1311 +; RV32I-FPELIM-NEXT: sw a0, 32(sp) +; RV32I-FPELIM-NEXT: lui a0, 688509 +; RV32I-FPELIM-NEXT: addi a5, a0, -2048 +; RV32I-FPELIM-NEXT: addi a2, sp, 32 +; RV32I-FPELIM-NEXT: addi a0, zero, 1 +; RV32I-FPELIM-NEXT: addi a1, zero, 11 +; RV32I-FPELIM-NEXT: addi a3, zero, 12 +; RV32I-FPELIM-NEXT: addi a4, zero, 13 +; RV32I-FPELIM-NEXT: addi a6, zero, 4 +; RV32I-FPELIM-NEXT: addi a7, zero, 14 +; RV32I-FPELIM-NEXT: call callee_aligned_stack +; RV32I-FPELIM-NEXT: lw ra, 60(sp) +; RV32I-FPELIM-NEXT: addi sp, sp, 64 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: caller_aligned_stack: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -64 +; RV32I-WITHFP-NEXT: sw ra, 60(sp) +; RV32I-WITHFP-NEXT: sw s0, 56(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 64 +; RV32I-WITHFP-NEXT: addi a0, zero, 18 +; RV32I-WITHFP-NEXT: sw a0, 24(sp) +; RV32I-WITHFP-NEXT: addi a0, zero, 17 +; RV32I-WITHFP-NEXT: sw a0, 20(sp) +; RV32I-WITHFP-NEXT: addi a0, zero, 16 +; RV32I-WITHFP-NEXT: sw a0, 16(sp) +; RV32I-WITHFP-NEXT: lui a0, 262236 +; RV32I-WITHFP-NEXT: addi a0, a0, 655 +; RV32I-WITHFP-NEXT: sw a0, 12(sp) +; RV32I-WITHFP-NEXT: lui a0, 377487 +; RV32I-WITHFP-NEXT: addi a0, a0, 1475 +; RV32I-WITHFP-NEXT: sw a0, 8(sp) +; RV32I-WITHFP-NEXT: addi a0, zero, 15 +; RV32I-WITHFP-NEXT: sw a0, 0(sp) +; RV32I-WITHFP-NEXT: lui a0, 262153 +; RV32I-WITHFP-NEXT: addi a0, a0, 491 +; RV32I-WITHFP-NEXT: sw a0, -20(s0) +; RV32I-WITHFP-NEXT: lui a0, 545260 +; RV32I-WITHFP-NEXT: addi a0, a0, -1967 +; RV32I-WITHFP-NEXT: sw a0, -24(s0) +; RV32I-WITHFP-NEXT: lui a0, 964690 +; RV32I-WITHFP-NEXT: addi a0, a0, -328 +; RV32I-WITHFP-NEXT: sw a0, -28(s0) +; RV32I-WITHFP-NEXT: lui a0, 335544 +; RV32I-WITHFP-NEXT: addi a0, a0, 1311 +; RV32I-WITHFP-NEXT: sw a0, -32(s0) +; RV32I-WITHFP-NEXT: lui a0, 688509 +; RV32I-WITHFP-NEXT: addi a5, a0, -2048 +; RV32I-WITHFP-NEXT: addi a2, s0, -32 +; RV32I-WITHFP-NEXT: addi a0, zero, 1 +; RV32I-WITHFP-NEXT: addi a1, zero, 11 +; RV32I-WITHFP-NEXT: addi a3, zero, 12 +; RV32I-WITHFP-NEXT: addi a4, zero, 13 +; RV32I-WITHFP-NEXT: addi a6, zero, 4 +; RV32I-WITHFP-NEXT: addi a7, zero, 14 +; RV32I-WITHFP-NEXT: call callee_aligned_stack +; RV32I-WITHFP-NEXT: lw s0, 56(sp) +; RV32I-WITHFP-NEXT: lw ra, 60(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 64 +; RV32I-WITHFP-NEXT: ret + %1 = call i32 @callee_aligned_stack(i32 1, i32 11, + fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, + i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16, + [2 x i32] [i32 17, i32 18]) + ret void +} + +define double @callee_small_scalar_ret() nounwind { +; RV32I-FPELIM-LABEL: callee_small_scalar_ret: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: mv a0, zero +; RV32I-FPELIM-NEXT: lui a1, 261888 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: callee_small_scalar_ret: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: mv a0, zero +; RV32I-WITHFP-NEXT: lui a1, 261888 +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + ret double 1.0 +} + +define i64 @caller_small_scalar_ret() nounwind { +; RV32I-FPELIM-LABEL: caller_small_scalar_ret: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi sp, sp, -16 +; RV32I-FPELIM-NEXT: sw ra, 12(sp) +; RV32I-FPELIM-NEXT: call callee_small_scalar_ret +; RV32I-FPELIM-NEXT: lw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi sp, sp, 16 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: caller_small_scalar_ret: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: call callee_small_scalar_ret +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %1 = call double @callee_small_scalar_ret() + %2 = bitcast double %1 to i64 + ret i64 %2 +} diff --git a/test/CodeGen/RISCV/calling-conv.ll b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll similarity index 90% rename from test/CodeGen/RISCV/calling-conv.ll rename to test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll index 8de77637760..3d552220daf 100644 --- a/test/CodeGen/RISCV/calling-conv.ll +++ b/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll @@ -4,96 +4,50 @@ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s -; As well as calling convention details, we check that ra and fp are -; consistently stored to fp-4 and fp-8. +; This file contains tests that should have identical output for the ilp32, +; ilp32f, and ilp32d ABIs. i.e. where no arguments are passed according to +; the floating point ABI. As well as calling convention details, we check that +; ra and fp are consistently stored to fp-4 and fp-8. -; Check that on RV32, i64 and double are passed in a pair of registers. Unlike +; Check that on RV32, i64 is passed in a pair of registers. Unlike ; the convention for varargs, this need not be an aligned pair. -define i32 @callee_scalars(i32 %a, i64 %b, i32 %c, i32 %d, double %e) nounwind { -; RV32I-FPELIM-LABEL: callee_scalars: +define i32 @callee_i64_in_regs(i32 %a, i64 %b) nounwind { +; RV32I-FPELIM-LABEL: callee_i64_in_regs: ; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -32 -; RV32I-FPELIM-NEXT: sw ra, 28(sp) -; RV32I-FPELIM-NEXT: sw s1, 24(sp) -; RV32I-FPELIM-NEXT: sw s2, 20(sp) -; RV32I-FPELIM-NEXT: sw s3, 16(sp) -; RV32I-FPELIM-NEXT: sw s4, 12(sp) -; RV32I-FPELIM-NEXT: mv s2, a4 -; RV32I-FPELIM-NEXT: mv s3, a3 -; RV32I-FPELIM-NEXT: mv s4, a1 -; RV32I-FPELIM-NEXT: mv s1, a0 -; RV32I-FPELIM-NEXT: mv a0, a5 -; RV32I-FPELIM-NEXT: mv a1, a6 -; RV32I-FPELIM-NEXT: call __fixdfsi -; RV32I-FPELIM-NEXT: add a1, s1, s4 -; RV32I-FPELIM-NEXT: add a1, a1, s3 -; RV32I-FPELIM-NEXT: add a1, a1, s2 -; RV32I-FPELIM-NEXT: add a0, a1, a0 -; RV32I-FPELIM-NEXT: lw s4, 12(sp) -; RV32I-FPELIM-NEXT: lw s3, 16(sp) -; RV32I-FPELIM-NEXT: lw s2, 20(sp) -; RV32I-FPELIM-NEXT: lw s1, 24(sp) -; RV32I-FPELIM-NEXT: lw ra, 28(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 32 +; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: callee_scalars: +; RV32I-WITHFP-LABEL: callee_i64_in_regs: ; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -32 -; RV32I-WITHFP-NEXT: sw ra, 28(sp) -; RV32I-WITHFP-NEXT: sw s0, 24(sp) -; RV32I-WITHFP-NEXT: sw s1, 20(sp) -; RV32I-WITHFP-NEXT: sw s2, 16(sp) -; RV32I-WITHFP-NEXT: sw s3, 12(sp) -; RV32I-WITHFP-NEXT: sw s4, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 32 -; RV32I-WITHFP-NEXT: mv s2, a4 -; RV32I-WITHFP-NEXT: mv s3, a3 -; RV32I-WITHFP-NEXT: mv s4, a1 -; RV32I-WITHFP-NEXT: mv s1, a0 -; RV32I-WITHFP-NEXT: mv a0, a5 -; RV32I-WITHFP-NEXT: mv a1, a6 -; RV32I-WITHFP-NEXT: call __fixdfsi -; RV32I-WITHFP-NEXT: add a1, s1, s4 -; RV32I-WITHFP-NEXT: add a1, a1, s3 -; RV32I-WITHFP-NEXT: add a1, a1, s2 -; RV32I-WITHFP-NEXT: add a0, a1, a0 -; RV32I-WITHFP-NEXT: lw s4, 8(sp) -; RV32I-WITHFP-NEXT: lw s3, 12(sp) -; RV32I-WITHFP-NEXT: lw s2, 16(sp) -; RV32I-WITHFP-NEXT: lw s1, 20(sp) -; RV32I-WITHFP-NEXT: lw s0, 24(sp) -; RV32I-WITHFP-NEXT: lw ra, 28(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 32 +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: add a0, a0, a1 +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: ret %b_trunc = trunc i64 %b to i32 - %e_fptosi = fptosi double %e to i32 %1 = add i32 %a, %b_trunc - %2 = add i32 %1, %c - %3 = add i32 %2, %d - %4 = add i32 %3, %e_fptosi - ret i32 %4 + ret i32 %1 } -define i32 @caller_scalars() nounwind { -; RV32I-FPELIM-LABEL: caller_scalars: +define i32 @caller_i64_in_regs() nounwind { +; RV32I-FPELIM-LABEL: caller_i64_in_regs: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: mv a2, zero -; RV32I-FPELIM-NEXT: addi a3, zero, 3 -; RV32I-FPELIM-NEXT: addi a4, zero, 4 -; RV32I-FPELIM-NEXT: mv a5, zero -; RV32I-FPELIM-NEXT: lui a6, 262464 -; RV32I-FPELIM-NEXT: call callee_scalars +; RV32I-FPELIM-NEXT: call callee_i64_in_regs ; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret ; -; RV32I-WITHFP-LABEL: caller_scalars: +; RV32I-WITHFP-LABEL: caller_i64_in_regs: ; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: sw ra, 12(sp) @@ -102,19 +56,125 @@ define i32 @caller_scalars() nounwind { ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: mv a2, zero -; RV32I-WITHFP-NEXT: addi a3, zero, 3 -; RV32I-WITHFP-NEXT: addi a4, zero, 4 -; RV32I-WITHFP-NEXT: mv a5, zero -; RV32I-WITHFP-NEXT: lui a6, 262464 -; RV32I-WITHFP-NEXT: call callee_scalars +; RV32I-WITHFP-NEXT: call callee_i64_in_regs +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %1 = call i32 @callee_i64_in_regs(i32 1, i64 2) + ret i32 %1 +} + +; Check that the stack is used once the GPRs are exhausted + +define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i64 %g, i32 %h) nounwind { +; RV32I-FPELIM-LABEL: callee_many_scalars: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: lw t0, 0(sp) +; RV32I-FPELIM-NEXT: xor a4, a4, t0 +; RV32I-FPELIM-NEXT: xor a3, a3, a7 +; RV32I-FPELIM-NEXT: or a3, a3, a4 +; RV32I-FPELIM-NEXT: lui a4, 16 +; RV32I-FPELIM-NEXT: addi a4, a4, -1 +; RV32I-FPELIM-NEXT: and a1, a1, a4 +; RV32I-FPELIM-NEXT: andi a0, a0, 255 +; RV32I-FPELIM-NEXT: add a0, a0, a1 +; RV32I-FPELIM-NEXT: add a0, a0, a2 +; RV32I-FPELIM-NEXT: seqz a1, a3 +; RV32I-FPELIM-NEXT: add a0, a1, a0 +; RV32I-FPELIM-NEXT: add a0, a0, a5 +; RV32I-FPELIM-NEXT: add a0, a0, a6 +; RV32I-FPELIM-NEXT: lw a1, 4(sp) +; RV32I-FPELIM-NEXT: add a0, a0, a1 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: callee_many_scalars: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: lw t0, 0(s0) +; RV32I-WITHFP-NEXT: xor a4, a4, t0 +; RV32I-WITHFP-NEXT: xor a3, a3, a7 +; RV32I-WITHFP-NEXT: or a3, a3, a4 +; RV32I-WITHFP-NEXT: lui a4, 16 +; RV32I-WITHFP-NEXT: addi a4, a4, -1 +; RV32I-WITHFP-NEXT: and a1, a1, a4 +; RV32I-WITHFP-NEXT: andi a0, a0, 255 +; RV32I-WITHFP-NEXT: add a0, a0, a1 +; RV32I-WITHFP-NEXT: add a0, a0, a2 +; RV32I-WITHFP-NEXT: seqz a1, a3 +; RV32I-WITHFP-NEXT: add a0, a1, a0 +; RV32I-WITHFP-NEXT: add a0, a0, a5 +; RV32I-WITHFP-NEXT: add a0, a0, a6 +; RV32I-WITHFP-NEXT: lw a1, 4(s0) +; RV32I-WITHFP-NEXT: add a0, a0, a1 +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %a_ext = zext i8 %a to i32 + %b_ext = zext i16 %b to i32 + %1 = add i32 %a_ext, %b_ext + %2 = add i32 %1, %c + %3 = icmp eq i64 %d, %g + %4 = zext i1 %3 to i32 + %5 = add i32 %4, %2 + %6 = add i32 %5, %e + %7 = add i32 %6, %f + %8 = add i32 %7, %h + ret i32 %8 +} + +define i32 @caller_many_scalars() nounwind { +; RV32I-FPELIM-LABEL: caller_many_scalars: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi sp, sp, -16 +; RV32I-FPELIM-NEXT: sw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 8 +; RV32I-FPELIM-NEXT: sw a0, 4(sp) +; RV32I-FPELIM-NEXT: sw zero, 0(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 1 +; RV32I-FPELIM-NEXT: addi a1, zero, 2 +; RV32I-FPELIM-NEXT: addi a2, zero, 3 +; RV32I-FPELIM-NEXT: addi a3, zero, 4 +; RV32I-FPELIM-NEXT: mv a4, zero +; RV32I-FPELIM-NEXT: addi a5, zero, 5 +; RV32I-FPELIM-NEXT: addi a6, zero, 6 +; RV32I-FPELIM-NEXT: addi a7, zero, 7 +; RV32I-FPELIM-NEXT: call callee_many_scalars +; RV32I-FPELIM-NEXT: lw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi sp, sp, 16 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: caller_many_scalars: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: addi a0, zero, 8 +; RV32I-WITHFP-NEXT: sw a0, 4(sp) +; RV32I-WITHFP-NEXT: sw zero, 0(sp) +; RV32I-WITHFP-NEXT: addi a0, zero, 1 +; RV32I-WITHFP-NEXT: addi a1, zero, 2 +; RV32I-WITHFP-NEXT: addi a2, zero, 3 +; RV32I-WITHFP-NEXT: addi a3, zero, 4 +; RV32I-WITHFP-NEXT: mv a4, zero +; RV32I-WITHFP-NEXT: addi a5, zero, 5 +; RV32I-WITHFP-NEXT: addi a6, zero, 6 +; RV32I-WITHFP-NEXT: addi a7, zero, 7 +; RV32I-WITHFP-NEXT: call callee_many_scalars ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: ret - %1 = call i32 @callee_scalars(i32 1, i64 2, i32 3, i32 4, double 5.000000e+00) + %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8) ret i32 %1 } + ; Check that i128 and fp128 are passed indirectly define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind { @@ -219,10 +279,11 @@ define i32 @caller_large_scalars() nounwind { ret i32 %1 } -; Must keep define on a single line due to an update_llc_test_checks.py limitation -define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i128 %h, i32 %i, fp128 %j) nounwind { ; Check that arguments larger than 2*xlen are handled correctly when their ; address is passed on the stack rather than in memory + +; Must keep define on a single line due to an update_llc_test_checks.py limitation +define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i128 %h, i32 %i, fp128 %j) nounwind { ; RV32I-FPELIM-LABEL: callee_large_scalars_exhausted_regs: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: lw a0, 4(sp) @@ -385,115 +446,6 @@ define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind { ret i32 %3 } -; Check that the stack is used once the GPRs are exhausted - -define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i64 %g, i32 %h) nounwind { -; RV32I-FPELIM-LABEL: callee_many_scalars: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: lw t0, 0(sp) -; RV32I-FPELIM-NEXT: xor a4, a4, t0 -; RV32I-FPELIM-NEXT: xor a3, a3, a7 -; RV32I-FPELIM-NEXT: or a3, a3, a4 -; RV32I-FPELIM-NEXT: lui a4, 16 -; RV32I-FPELIM-NEXT: addi a4, a4, -1 -; RV32I-FPELIM-NEXT: and a1, a1, a4 -; RV32I-FPELIM-NEXT: andi a0, a0, 255 -; RV32I-FPELIM-NEXT: add a0, a0, a1 -; RV32I-FPELIM-NEXT: add a0, a0, a2 -; RV32I-FPELIM-NEXT: seqz a1, a3 -; RV32I-FPELIM-NEXT: add a0, a1, a0 -; RV32I-FPELIM-NEXT: add a0, a0, a5 -; RV32I-FPELIM-NEXT: add a0, a0, a6 -; RV32I-FPELIM-NEXT: lw a1, 4(sp) -; RV32I-FPELIM-NEXT: add a0, a0, a1 -; RV32I-FPELIM-NEXT: ret -; -; RV32I-WITHFP-LABEL: callee_many_scalars: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -16 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lw t0, 0(s0) -; RV32I-WITHFP-NEXT: xor a4, a4, t0 -; RV32I-WITHFP-NEXT: xor a3, a3, a7 -; RV32I-WITHFP-NEXT: or a3, a3, a4 -; RV32I-WITHFP-NEXT: lui a4, 16 -; RV32I-WITHFP-NEXT: addi a4, a4, -1 -; RV32I-WITHFP-NEXT: and a1, a1, a4 -; RV32I-WITHFP-NEXT: andi a0, a0, 255 -; RV32I-WITHFP-NEXT: add a0, a0, a1 -; RV32I-WITHFP-NEXT: add a0, a0, a2 -; RV32I-WITHFP-NEXT: seqz a1, a3 -; RV32I-WITHFP-NEXT: add a0, a1, a0 -; RV32I-WITHFP-NEXT: add a0, a0, a5 -; RV32I-WITHFP-NEXT: add a0, a0, a6 -; RV32I-WITHFP-NEXT: lw a1, 4(s0) -; RV32I-WITHFP-NEXT: add a0, a0, a1 -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 16 -; RV32I-WITHFP-NEXT: ret - %a_ext = zext i8 %a to i32 - %b_ext = zext i16 %b to i32 - %1 = add i32 %a_ext, %b_ext - %2 = add i32 %1, %c - %3 = icmp eq i64 %d, %g - %4 = zext i1 %3 to i32 - %5 = add i32 %4, %2 - %6 = add i32 %5, %e - %7 = add i32 %6, %f - %8 = add i32 %7, %h - ret i32 %8 -} - -define i32 @caller_many_scalars() nounwind { -; RV32I-FPELIM-LABEL: caller_many_scalars: -; RV32I-FPELIM: # %bb.0: -; RV32I-FPELIM-NEXT: addi sp, sp, -16 -; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 8 -; RV32I-FPELIM-NEXT: sw a0, 4(sp) -; RV32I-FPELIM-NEXT: sw zero, 0(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 1 -; RV32I-FPELIM-NEXT: addi a1, zero, 2 -; RV32I-FPELIM-NEXT: addi a2, zero, 3 -; RV32I-FPELIM-NEXT: addi a3, zero, 4 -; RV32I-FPELIM-NEXT: mv a4, zero -; RV32I-FPELIM-NEXT: addi a5, zero, 5 -; RV32I-FPELIM-NEXT: addi a6, zero, 6 -; RV32I-FPELIM-NEXT: addi a7, zero, 7 -; RV32I-FPELIM-NEXT: call callee_many_scalars -; RV32I-FPELIM-NEXT: lw ra, 12(sp) -; RV32I-FPELIM-NEXT: addi sp, sp, 16 -; RV32I-FPELIM-NEXT: ret -; -; RV32I-WITHFP-LABEL: caller_many_scalars: -; RV32I-WITHFP: # %bb.0: -; RV32I-WITHFP-NEXT: addi sp, sp, -16 -; RV32I-WITHFP-NEXT: sw ra, 12(sp) -; RV32I-WITHFP-NEXT: sw s0, 8(sp) -; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: addi a0, zero, 8 -; RV32I-WITHFP-NEXT: sw a0, 4(sp) -; RV32I-WITHFP-NEXT: sw zero, 0(sp) -; RV32I-WITHFP-NEXT: addi a0, zero, 1 -; RV32I-WITHFP-NEXT: addi a1, zero, 2 -; RV32I-WITHFP-NEXT: addi a2, zero, 3 -; RV32I-WITHFP-NEXT: addi a3, zero, 4 -; RV32I-WITHFP-NEXT: mv a4, zero -; RV32I-WITHFP-NEXT: addi a5, zero, 5 -; RV32I-WITHFP-NEXT: addi a6, zero, 6 -; RV32I-WITHFP-NEXT: addi a7, zero, 7 -; RV32I-WITHFP-NEXT: call callee_many_scalars -; RV32I-WITHFP-NEXT: lw s0, 8(sp) -; RV32I-WITHFP-NEXT: lw ra, 12(sp) -; RV32I-WITHFP-NEXT: addi sp, sp, 16 -; RV32I-WITHFP-NEXT: ret - %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8) - ret i32 %1 -} - ; Check passing of coerced integer arrays %struct.small = type { i32, i32* } @@ -649,8 +601,8 @@ define i32 @caller_large_struct() nounwind { ; Check 2x*xlen values are aligned appropriately when passed on the stack ; Must keep define on a single line due to an update_llc_test_checks.py limitation -define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, double %i, i32 %j, [2 x i32] %k) nounwind { -; The double should be 8-byte aligned on the stack, but the two-element array +define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, i64 %i, i32 %j, [2 x i32] %k) nounwind { +; The i64 should be 8-byte aligned on the stack, but the two-element array ; should only be 4-byte aligned ; RV32I-FPELIM-LABEL: callee_aligned_stack: ; RV32I-FPELIM: # %bb.0: @@ -690,33 +642,29 @@ define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 % %2 = trunc i128 %1 to i32 %3 = add i32 %2, %g %4 = add i32 %3, %h - %5 = bitcast double %i to i64 - %6 = trunc i64 %5 to i32 - %7 = add i32 %4, %6 - %8 = add i32 %7, %j - %9 = extractvalue [2 x i32] %k, 0 - %10 = add i32 %8, %9 - ret i32 %10 + %5 = trunc i64 %i to i32 + %6 = add i32 %4, %5 + %7 = add i32 %6, %j + %8 = extractvalue [2 x i32] %k, 0 + %9 = add i32 %7, %8 + ret i32 %9 } define void @caller_aligned_stack() nounwind { -; The double should be 8-byte aligned on the stack, but the two-element array +; The i64 should be 8-byte aligned on the stack, but the two-element array ; should only be 4-byte aligned ; RV32I-FPELIM-LABEL: caller_aligned_stack: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -64 ; RV32I-FPELIM-NEXT: sw ra, 60(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 18 +; RV32I-FPELIM-NEXT: addi a0, zero, 19 ; RV32I-FPELIM-NEXT: sw a0, 24(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 17 +; RV32I-FPELIM-NEXT: addi a0, zero, 18 ; RV32I-FPELIM-NEXT: sw a0, 20(sp) -; RV32I-FPELIM-NEXT: addi a0, zero, 16 +; RV32I-FPELIM-NEXT: addi a0, zero, 17 ; RV32I-FPELIM-NEXT: sw a0, 16(sp) -; RV32I-FPELIM-NEXT: lui a0, 262236 -; RV32I-FPELIM-NEXT: addi a0, a0, 655 -; RV32I-FPELIM-NEXT: sw a0, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, 377487 -; RV32I-FPELIM-NEXT: addi a0, a0, 1475 +; RV32I-FPELIM-NEXT: sw zero, 12(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 16 ; RV32I-FPELIM-NEXT: sw a0, 8(sp) ; RV32I-FPELIM-NEXT: addi a0, zero, 15 ; RV32I-FPELIM-NEXT: sw a0, 0(sp) @@ -752,17 +700,14 @@ define void @caller_aligned_stack() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 60(sp) ; RV32I-WITHFP-NEXT: sw s0, 56(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 64 -; RV32I-WITHFP-NEXT: addi a0, zero, 18 +; RV32I-WITHFP-NEXT: addi a0, zero, 19 ; RV32I-WITHFP-NEXT: sw a0, 24(sp) -; RV32I-WITHFP-NEXT: addi a0, zero, 17 +; RV32I-WITHFP-NEXT: addi a0, zero, 18 ; RV32I-WITHFP-NEXT: sw a0, 20(sp) -; RV32I-WITHFP-NEXT: addi a0, zero, 16 +; RV32I-WITHFP-NEXT: addi a0, zero, 17 ; RV32I-WITHFP-NEXT: sw a0, 16(sp) -; RV32I-WITHFP-NEXT: lui a0, 262236 -; RV32I-WITHFP-NEXT: addi a0, a0, 655 -; RV32I-WITHFP-NEXT: sw a0, 12(sp) -; RV32I-WITHFP-NEXT: lui a0, 377487 -; RV32I-WITHFP-NEXT: addi a0, a0, 1475 +; RV32I-WITHFP-NEXT: sw zero, 12(sp) +; RV32I-WITHFP-NEXT: addi a0, zero, 16 ; RV32I-WITHFP-NEXT: sw a0, 8(sp) ; RV32I-WITHFP-NEXT: addi a0, zero, 15 ; RV32I-WITHFP-NEXT: sw a0, 0(sp) @@ -794,8 +739,8 @@ define void @caller_aligned_stack() nounwind { ; RV32I-WITHFP-NEXT: ret %1 = call i32 @callee_aligned_stack(i32 1, i32 11, fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, - i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16, - [2 x i32] [i32 17, i32 18]) + i64 20000000000, i32 14, i32 15, i64 16, i32 17, + [2 x i32] [i32 18, i32 19]) ret void } diff --git a/test/CodeGen/RISCV/calling-conv-ilp32.ll b/test/CodeGen/RISCV/calling-conv-ilp32.ll new file mode 100644 index 00000000000..7bc51271866 --- /dev/null +++ b/test/CodeGen/RISCV/calling-conv-ilp32.ll @@ -0,0 +1,194 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ +; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s + +; As well as calling convention details, we check that ra and fp are +; consistently stored to fp-4 and fp-8. + +; Any tests that would have identical output for some combination of the ilp32* +; ABIs belong in calling-conv-*-common.ll. This file contains tests that will +; have different output across those ABIs. i.e. where some arguments would be +; passed according to the floating point ABI. + +define i32 @callee_float_in_regs(i32 %a, float %b) nounwind { +; RV32I-FPELIM-LABEL: callee_float_in_regs: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi sp, sp, -16 +; RV32I-FPELIM-NEXT: sw ra, 12(sp) +; RV32I-FPELIM-NEXT: sw s1, 8(sp) +; RV32I-FPELIM-NEXT: mv s1, a0 +; RV32I-FPELIM-NEXT: mv a0, a1 +; RV32I-FPELIM-NEXT: call __fixsfsi +; RV32I-FPELIM-NEXT: add a0, s1, a0 +; RV32I-FPELIM-NEXT: lw s1, 8(sp) +; RV32I-FPELIM-NEXT: lw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi sp, sp, 16 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: callee_float_in_regs: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: sw s1, 4(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: mv s1, a0 +; RV32I-WITHFP-NEXT: mv a0, a1 +; RV32I-WITHFP-NEXT: call __fixsfsi +; RV32I-WITHFP-NEXT: add a0, s1, a0 +; RV32I-WITHFP-NEXT: lw s1, 4(sp) +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %b_fptosi = fptosi float %b to i32 + %1 = add i32 %a, %b_fptosi + ret i32 %1 +} + +define i32 @caller_float_in_regs() nounwind { +; RV32I-FPELIM-LABEL: caller_float_in_regs: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi sp, sp, -16 +; RV32I-FPELIM-NEXT: sw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 1 +; RV32I-FPELIM-NEXT: lui a1, 262144 +; RV32I-FPELIM-NEXT: call callee_float_in_regs +; RV32I-FPELIM-NEXT: lw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi sp, sp, 16 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: caller_float_in_regs: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: addi a0, zero, 1 +; RV32I-WITHFP-NEXT: lui a1, 262144 +; RV32I-WITHFP-NEXT: call callee_float_in_regs +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %1 = call i32 @callee_float_in_regs(i32 1, float 2.0) + ret i32 %1 +} + +define i32 @callee_float_on_stack(i64 %a, i64 %b, i64 %c, i64 %d, float %e) nounwind { +; RV32I-FPELIM-LABEL: callee_float_on_stack: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: lw a0, 0(sp) +; RV32I-FPELIM-NEXT: add a0, a6, a0 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: callee_float_on_stack: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: lw a0, 0(s0) +; RV32I-WITHFP-NEXT: add a0, a6, a0 +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %1 = trunc i64 %d to i32 + %2 = bitcast float %e to i32 + %3 = add i32 %1, %2 + ret i32 %3 +} + +define i32 @caller_float_on_stack() nounwind { +; RV32I-FPELIM-LABEL: caller_float_on_stack: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi sp, sp, -16 +; RV32I-FPELIM-NEXT: sw ra, 12(sp) +; RV32I-FPELIM-NEXT: lui a0, 264704 +; RV32I-FPELIM-NEXT: sw a0, 0(sp) +; RV32I-FPELIM-NEXT: addi a0, zero, 1 +; RV32I-FPELIM-NEXT: mv a1, zero +; RV32I-FPELIM-NEXT: addi a2, zero, 2 +; RV32I-FPELIM-NEXT: mv a3, zero +; RV32I-FPELIM-NEXT: addi a4, zero, 3 +; RV32I-FPELIM-NEXT: mv a5, zero +; RV32I-FPELIM-NEXT: addi a6, zero, 4 +; RV32I-FPELIM-NEXT: mv a7, zero +; RV32I-FPELIM-NEXT: call callee_float_on_stack +; RV32I-FPELIM-NEXT: lw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi sp, sp, 16 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: caller_float_on_stack: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: lui a0, 264704 +; RV32I-WITHFP-NEXT: sw a0, 0(sp) +; RV32I-WITHFP-NEXT: addi a0, zero, 1 +; RV32I-WITHFP-NEXT: mv a1, zero +; RV32I-WITHFP-NEXT: addi a2, zero, 2 +; RV32I-WITHFP-NEXT: mv a3, zero +; RV32I-WITHFP-NEXT: addi a4, zero, 3 +; RV32I-WITHFP-NEXT: mv a5, zero +; RV32I-WITHFP-NEXT: addi a6, zero, 4 +; RV32I-WITHFP-NEXT: mv a7, zero +; RV32I-WITHFP-NEXT: call callee_float_on_stack +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %1 = call i32 @callee_float_on_stack(i64 1, i64 2, i64 3, i64 4, float 5.0) + ret i32 %1 +} + +define float @callee_tiny_scalar_ret() nounwind { +; RV32I-FPELIM-LABEL: callee_tiny_scalar_ret: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: lui a0, 260096 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: callee_tiny_scalar_ret: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: lui a0, 260096 +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + ret float 1.0 +} + +define i32 @caller_tiny_scalar_ret() nounwind { +; RV32I-FPELIM-LABEL: caller_tiny_scalar_ret: +; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi sp, sp, -16 +; RV32I-FPELIM-NEXT: sw ra, 12(sp) +; RV32I-FPELIM-NEXT: call callee_tiny_scalar_ret +; RV32I-FPELIM-NEXT: lw ra, 12(sp) +; RV32I-FPELIM-NEXT: addi sp, sp, 16 +; RV32I-FPELIM-NEXT: ret +; +; RV32I-WITHFP-LABEL: caller_tiny_scalar_ret: +; RV32I-WITHFP: # %bb.0: +; RV32I-WITHFP-NEXT: addi sp, sp, -16 +; RV32I-WITHFP-NEXT: sw ra, 12(sp) +; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: call callee_tiny_scalar_ret +; RV32I-WITHFP-NEXT: lw s0, 8(sp) +; RV32I-WITHFP-NEXT: lw ra, 12(sp) +; RV32I-WITHFP-NEXT: addi sp, sp, 16 +; RV32I-WITHFP-NEXT: ret + %1 = call float @callee_tiny_scalar_ret() + %2 = bitcast float %1 to i32 + ret i32 %2 +} -- 2.11.0