From 628d758731693ef3bfd883279b86a3350d1e553c Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Tue, 18 Oct 2016 10:55:22 +0300 Subject: [PATCH] ARM: DRA7: hwmod: Add data for AES IP DRA7 SoC contains AES crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks. Signed-off-by: Joel Fernandes Signed-off-by: Lokesh Vutla [t-kristo@ti.com: squash in support for both AES1 and AES2 cores] Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 62 +++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index e89a7ecdc567..4988a9e1d3d3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -690,6 +690,50 @@ static struct omap_hwmod dra7xx_dss_hdmi_hwmod = { .parent_hwmod = &dra7xx_dss_hwmod, }; +/* AES (the 'P' (public) device) */ +static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = { + .rev_offs = 0x0080, + .sysc_offs = 0x0084, + .syss_offs = 0x0088, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class dra7xx_aes_hwmod_class = { + .name = "aes", + .sysc = &dra7xx_aes_sysc, + .rev = 2, +}; + +/* AES1 */ +static struct omap_hwmod dra7xx_aes1_hwmod = { + .name = "aes1", + .class = &dra7xx_aes_hwmod_class, + .clkdm_name = "l4sec_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* AES2 */ +static struct omap_hwmod dra7xx_aes2_hwmod = { + .name = "aes2", + .class = &dra7xx_aes_hwmod_class, + .clkdm_name = "l4sec_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + /* * 'elm' class * @@ -2957,6 +3001,22 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> aes1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_aes1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> aes2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_aes2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per2 -> mcasp1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { .master = &dra7xx_l4_per2_hwmod, @@ -3836,6 +3896,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__dss, &dra7xx_l3_main_1__dispc, &dra7xx_l3_main_1__hdmi, + &dra7xx_l3_main_1__aes1, + &dra7xx_l3_main_1__aes2, &dra7xx_l4_per1__elm, &dra7xx_l4_wkup__gpio1, &dra7xx_l4_per1__gpio2, -- 2.11.0