From 65971bbfd7306611031cfc892195ece5bfcbaa1b Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 30 Dec 2014 20:42:23 +0000 Subject: [PATCH] [Hexagon] Adding indexed stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225005 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrInfo.cpp | 15 +- lib/Target/Hexagon/HexagonInstrInfoV4.td | 233 +++++++++++++++++++++---------- test/MC/Disassembler/Hexagon/nv_st.txt | 55 ++++++++ test/MC/Disassembler/Hexagon/st.txt | 60 ++++++++ 4 files changed, 282 insertions(+), 81 deletions(-) create mode 100644 test/MC/Disassembler/Hexagon/nv_st.txt diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index ffc59d25d03..933a2d8dacd 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1422,31 +1422,32 @@ isConditionalStore (const MachineInstr* MI) const { default: return false; case Hexagon::STrib_imm_cPt_V4 : case Hexagon::STrib_imm_cNotPt_V4 : - case Hexagon::STrib_indexed_shl_cPt_V4 : - case Hexagon::STrib_indexed_shl_cNotPt_V4 : + case Hexagon::S4_pstorerbt_rr: + case Hexagon::S4_pstorerbf_rr: case Hexagon::S2_pstorerbt_io: case Hexagon::S2_pstorerbf_io: case Hexagon::S2_pstorerbt_pi: case Hexagon::S2_pstorerbf_pi: case Hexagon::S2_pstorerdt_io: case Hexagon::S2_pstorerdf_io: - case Hexagon::STrid_indexed_shl_cPt_V4 : + case Hexagon::S4_pstorerdt_rr: + case Hexagon::S4_pstorerdf_rr: case Hexagon::S2_pstorerdt_pi: case Hexagon::S2_pstorerdf_pi: case Hexagon::S2_pstorerht_io: case Hexagon::S2_pstorerhf_io: case Hexagon::STrih_imm_cPt_V4 : case Hexagon::STrih_imm_cNotPt_V4 : - case Hexagon::STrih_indexed_shl_cPt_V4 : - case Hexagon::STrih_indexed_shl_cNotPt_V4 : + case Hexagon::S4_pstorerht_rr: + case Hexagon::S4_pstorerhf_rr: case Hexagon::S2_pstorerht_pi: case Hexagon::S2_pstorerhf_pi: case Hexagon::S2_pstorerit_io: case Hexagon::S2_pstorerif_io: case Hexagon::STriw_imm_cPt_V4 : case Hexagon::STriw_imm_cNotPt_V4 : - case Hexagon::STriw_indexed_shl_cPt_V4 : - case Hexagon::STriw_indexed_shl_cNotPt_V4 : + case Hexagon::S4_pstorerit_rr: + case Hexagon::S4_pstorerif_rr: case Hexagon::S2_pstorerit_pi: case Hexagon::S2_pstorerif_pi: return QRI.Subtarget.hasV4TOps(); diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 894d67d4c4c..3ba0bf5555c 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -636,124 +636,209 @@ def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>; def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>; //===----------------------------------------------------------------------===// -// multiclass for store instructions with base + register offset addressing -// mode +// Template classes for the non-predicated store instructions with +// base + register offset addressing mode //===----------------------------------------------------------------------===// -multiclass ST_Idxd_shl_Pbase { - let isPredicatedNew = isPredNew in - def NAME : STInst2<(outs), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, - RC:$src5), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5", - []>, - Requires<[HasV4T]>; -} +let isPredicable = 1 in +class T_store_rr MajOp, bit isH> + : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt), + mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""), + [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel { -multiclass ST_Idxd_shl_Pred { - let isPredicatedFalse = PredNot in { - defm _c#NAME : ST_Idxd_shl_Pbase; - // Predicate new - defm _cdn#NAME : ST_Idxd_shl_Pbase; + bits<5> Rs; + bits<5> Ru; + bits<2> u2; + bits<5> Rt; + + let IClass = 0b0011; + + let Inst{27-24} = 0b1011; + let Inst{23-21} = MajOp; + let Inst{20-16} = Rs; + let Inst{12-8} = Ru; + let Inst{13} = u2{1}; + let Inst{7} = u2{0}; + let Inst{4-0} = Rt; + } + +//===----------------------------------------------------------------------===// +// Template classes for the predicated store instructions with +// base + register offset addressing mode +//===----------------------------------------------------------------------===// +let isPredicated = 1 in +class T_pstore_rr MajOp, + bit isNot, bit isPredNew, bit isH> + : STInst <(outs), + (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt), + + !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ", + ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""), + [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{ + bits<2> Pv; + bits<5> Rs; + bits<5> Ru; + bits<2> u2; + bits<5> Rt; + + let isPredicatedFalse = isNot; + let isPredicatedNew = isPredNew; + + let IClass = 0b0011; + + let Inst{27-26} = 0b01; + let Inst{25} = isPredNew; + let Inst{24} = isNot; + let Inst{23-21} = MajOp; + let Inst{20-16} = Rs; + let Inst{12-8} = Ru; + let Inst{13} = u2{1}; + let Inst{7} = u2{0}; + let Inst{6-5} = Pv; + let Inst{4-0} = Rt; + } + +//===----------------------------------------------------------------------===// +// Template classes for the new-value store instructions with +// base + register offset addressing mode +//===----------------------------------------------------------------------===// +let isPredicable = 1, isNewValue = 1, opNewValue = 3 in +class T_store_new_rr MajOp> : + NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt), + mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new", + [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel { + + bits<5> Rs; + bits<5> Ru; + bits<2> u2; + bits<3> Nt; + + let IClass = 0b0011; + + let Inst{27-21} = 0b1011101; + let Inst{20-16} = Rs; + let Inst{12-8} = Ru; + let Inst{13} = u2{1}; + let Inst{7} = u2{0}; + let Inst{4-3} = MajOp; + let Inst{2-0} = Nt; } -} +//===----------------------------------------------------------------------===// +// Template classes for the predicated new-value store instructions with +// base + register offset addressing mode +//===----------------------------------------------------------------------===// +let isPredicated = 1, isNewValue = 1, opNewValue = 4 in +class T_pstore_new_rr MajOp, bit isNot, bit isPredNew> + : NVInst<(outs), + (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt), + !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ", + ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new", + [], "", V4LDST_tc_st_SLOT0>, AddrModeRel { + bits<2> Pv; + bits<5> Rs; + bits<5> Ru; + bits<2> u2; + bits<3> Nt; + + let isPredicatedFalse = isNot; + let isPredicatedNew = isPredNew; + + let IClass = 0b0011; + let Inst{27-26} = 0b01; + let Inst{25} = isPredNew; + let Inst{24} = isNot; + let Inst{23-21} = 0b101; + let Inst{20-16} = Rs; + let Inst{12-8} = Ru; + let Inst{13} = u2{1}; + let Inst{7} = u2{0}; + let Inst{6-5} = Pv; + let Inst{4-3} = MajOp; + let Inst{2-0} = Nt; + } + +//===----------------------------------------------------------------------===// +// multiclass for store instructions with base + register offset addressing +// mode +//===----------------------------------------------------------------------===// let isNVStorable = 1 in -multiclass ST_Idxd_shl { +multiclass ST_Idxd_shl MajOp, bit isH = 0> { let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in { - let isPredicable = 1 in - def NAME#_V4 : STInst2<(outs), - (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4), - mnemonic#"($src1+$src2<<#$src3) = $src4", - []>, - Requires<[HasV4T]>; + def S4_#NAME#_rr : T_store_rr ; - let isPredicated = 1 in { - defm Pt_V4 : ST_Idxd_shl_Pred; - defm NotPt_V4 : ST_Idxd_shl_Pred; - } + // Predicated + def S4_p#NAME#t_rr : T_pstore_rr ; + def S4_p#NAME#f_rr : T_pstore_rr ; + + // Predicated new + def S4_p#NAME#tnew_rr : T_pstore_rr ; + def S4_p#NAME#fnew_rr : T_pstore_rr ; } } +//===----------------------------------------------------------------------===// // multiclass for new-value store instructions with base + register offset // addressing mode. -multiclass ST_Idxd_shl_Pbase_nv { - let isPredicatedNew = isPredNew in - def NAME#_nv_V4 : NVInst_V4<(outs), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, - RC:$src5), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new", - []>, - Requires<[HasV4T]>; -} - -multiclass ST_Idxd_shl_Pred_nv { - let isPredicatedFalse = PredNot in { - defm _c#NAME : ST_Idxd_shl_Pbase_nv; - // Predicate new - defm _cdn#NAME : ST_Idxd_shl_Pbase_nv; - } -} - +//===----------------------------------------------------------------------===// let mayStore = 1, isNVStore = 1 in -multiclass ST_Idxd_shl_nv { +multiclass ST_Idxd_shl_nv MajOp> { let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in { - let isPredicable = 1 in - def NAME#_nv_V4 : NVInst_V4<(outs), - (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4), - mnemonic#"($src1+$src2<<#$src3) = $src4.new", - []>, - Requires<[HasV4T]>; + def S4_#NAME#new_rr : T_store_new_rr; - let isPredicated = 1 in { - defm Pt : ST_Idxd_shl_Pred_nv; - defm NotPt : ST_Idxd_shl_Pred_nv; - } + // Predicated + def S4_p#NAME#newt_rr : T_pstore_new_rr ; + def S4_p#NAME#newf_rr : T_pstore_new_rr ; + + // Predicated new + def S4_p#NAME#newtnew_rr : T_pstore_new_rr ; + def S4_p#NAME#newfnew_rr : T_pstore_new_rr ; } } -let addrMode = BaseRegOffset, hasSideEffects = 0, -validSubTargets = HasV4SubT in { +let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0, + isCodeGenOnly = 0 in { let accessSize = ByteAccess in - defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>, - ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel; + defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>, + ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>; let accessSize = HalfWordAccess in - defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>, - ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel; + defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>, + ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>; let accessSize = WordAccess in - defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>, - ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel; + defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>, + ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>; let isNVStorable = 0, accessSize = DoubleWordAccess in - defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel; + defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>; + + let isNVStorable = 0, accessSize = HalfWordAccess in + defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>; } let Predicates = [HasV4T], AddedComplexity = 10 in { def : Pat<(truncstorei8 (i32 IntRegs:$src4), (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))), - (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, + (S4_storerb_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$src3, IntRegs:$src4)>; def : Pat<(truncstorei16 (i32 IntRegs:$src4), (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))), - (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, + (S4_storerh_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$src3, IntRegs:$src4)>; def : Pat<(store (i32 IntRegs:$src4), (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))), - (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, + (S4_storeri_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$src3, IntRegs:$src4)>; def : Pat<(store (i64 DoubleRegs:$src4), (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))), - (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, + (S4_storerd_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$src3, DoubleRegs:$src4)>; } diff --git a/test/MC/Disassembler/Hexagon/nv_st.txt b/test/MC/Disassembler/Hexagon/nv_st.txt new file mode 100644 index 00000000000..d53e64d7df2 --- /dev/null +++ b/test/MC/Disassembler/Hexagon/nv_st.txt @@ -0,0 +1,55 @@ +# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s + +0x1f 0x40 0x7f 0x70 0x82 0xf5 0xb1 0x3b +# CHECK: r31 = r31 +# CHECK-NEXT: memb(r17 + r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34 +# CHECK: r31 = r31 +# CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x35 +# CHECK: r31 = r31 +# CHECK-NEXT: if (!p3) memb(r17+r21<<#3) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x36 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (p3.new) memb(r17+r21<<#3) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x37 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r2.new + +0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b +# CHECK: r31 = r31 +# CHECK-NEXT: memh(r17 + r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34 +# CHECK: r31 = r31 +# CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x35 +# CHECK: r31 = r31 +# CHECK-NEXT: if (!p3) memh(r17+r21<<#3) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x36 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (p3.new) memh(r17+r21<<#3) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x37 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r2.new + +0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b +# CHECK: r31 = r31 +# CHECK-NEXT: memw(r17 + r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34 +# CHECK: r31 = r31 +# CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new +0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x35 +# CHECK: r31 = r31 +# CHECK-NEXT: if (!p3) memw(r17+r21<<#3) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x36 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (p3.new) memw(r17+r21<<#3) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x37 +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r2.new diff --git a/test/MC/Disassembler/Hexagon/st.txt b/test/MC/Disassembler/Hexagon/st.txt index 09a677ad88f..911326c8725 100644 --- a/test/MC/Disassembler/Hexagon/st.txt +++ b/test/MC/Disassembler/Hexagon/st.txt @@ -1,5 +1,7 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +0x9e 0xf5 0xd1 0x3b +# CHECK: memd(r17 + r21<<#3) = r31:30 0x15 0xd4 0xd1 0xa1 # CHECK: memd(r17+#168) = r21:20 0x02 0xf4 0xd1 0xa9 @@ -12,6 +14,16 @@ # CHECK: memd(r17++m1) = r21:20 0x00 0xf4 0xd1 0xaf # CHECK: memd(r17 ++ m1:brev) = r21:20 +0xfe 0xf5 0xd1 0x34 +# CHECK: if (p3) memd(r17+r21<<#3) = r31:30 +0xfe 0xf5 0xd1 0x35 +# CHECK: if (!p3) memd(r17+r21<<#3) = r31:30 +0x03 0x40 0x45 0x85 0xfe 0xf5 0xd1 0x36 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memd(r17+r21<<#3) = r31:30 +0x03 0x40 0x45 0x85 0xfe 0xf5 0xd1 0x37 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memd(r17+r21<<#3) = r31:30 0xab 0xde 0xd1 0x40 # CHECK: if (p3) memd(r17+#168) = r31:30 0xab 0xde 0xd1 0x44 @@ -33,6 +45,8 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) memd(r17++#40) = r21:20 +0x9f 0xf5 0x11 0x3b +# CHECK: memb(r17 + r21<<#3) = r31 0x15 0xd5 0x11 0xa1 # CHECK: memb(r17+#21) = r21 0x02 0xf5 0x11 0xa9 @@ -45,6 +59,16 @@ # CHECK: memb(r17++m1) = r21 0x00 0xf5 0x11 0xaf # CHECK: memb(r17 ++ m1:brev) = r21 +0xff 0xf5 0x11 0x34 +# CHECK: if (p3) memb(r17+r21<<#3) = r31 +0xff 0xf5 0x11 0x35 +# CHECK: if (!p3) memb(r17+r21<<#3) = r31 +0x03 0x40 0x45 0x85 0xff 0xf5 0x11 0x36 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memb(r17+r21<<#3) = r31 +0x03 0x40 0x45 0x85 0xff 0xf5 0x11 0x37 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r31 0xab 0xdf 0x11 0x40 # CHECK: if (p3) memb(r17+#21) = r31 0xab 0xdf 0x11 0x44 @@ -66,6 +90,10 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21 +0x9f 0xf5 0x51 0x3b +# CHECK: memh(r17 + r21<<#3) = r31 +0x9f 0xf5 0x71 0x3b +# CHECK: memh(r17 + r21<<#3) = r31.h 0x15 0xdf 0x51 0xa1 # CHECK: memh(r17+#42) = r31 0x15 0xdf 0x71 0xa1 @@ -90,6 +118,26 @@ # CHECK: memh(r17 ++ m1:brev) = r21 0x00 0xf5 0x71 0xaf # CHECK: memh(r17 ++ m1:brev) = r21.h +0xff 0xf5 0x51 0x34 +# CHECK: if (p3) memh(r17+r21<<#3) = r31 +0xff 0xf5 0x71 0x34 +# CHECK: if (p3) memh(r17+r21<<#3) = r31.h +0xff 0xf5 0x51 0x35 +# CHECK: if (!p3) memh(r17+r21<<#3) = r31 +0xff 0xf5 0x71 0x35 +# CHECK: if (!p3) memh(r17+r21<<#3) = r31.h +0x03 0x40 0x45 0x85 0xff 0xf5 0x51 0x36 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memh(r17+r21<<#3) = r31 +0x03 0x40 0x45 0x85 0xff 0xf5 0x71 0x36 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memh(r17+r21<<#3) = r31.h +0x03 0x40 0x45 0x85 0xff 0xf5 0x51 0x37 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r31 +0x03 0x40 0x45 0x85 0xff 0xf5 0x71 0x37 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r31.h 0xfb 0xd5 0x51 0x40 # CHECK: if (p3) memh(r17+#62) = r21 0xfb 0xd5 0x71 0x40 @@ -131,6 +179,8 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21.h +0x9f 0xf5 0x91 0x3b +# CHECK: memw(r17 + r21<<#3) = r31 0x15 0xdf 0x91 0xa1 # CHECK: memw(r17+#84) = r31 0x02 0xf5 0x91 0xa9 @@ -143,6 +193,16 @@ # CHECK: memw(r17++m1) = r21 0x00 0xf5 0x91 0xaf # CHECK: memw(r17 ++ m1:brev) = r21 +0xff 0xf5 0x91 0x34 +# CHECK: if (p3) memw(r17+r21<<#3) = r31 +0xff 0xf5 0x91 0x35 +# CHECK: if (!p3) memw(r17+r21<<#3) = r31 +0x03 0x40 0x45 0x85 0xff 0xf5 0x91 0x36 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memw(r17+r21<<#3) = r31 +0x03 0x40 0x45 0x85 0xff 0xf5 0x91 0x37 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r31 0xab 0xdf 0x91 0x40 # CHECK: if (p3) memw(r17+#84) = r31 0xab 0xdf 0x91 0x44 -- 2.11.0