From 697f2a80e9c58eca904a1414bff8114c9311e94c Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Fri, 15 Feb 2019 10:50:02 +0000 Subject: [PATCH] [ARM GlobalISel] Style fix. NFCI Add the opcode for ADDrr / t2ADDrr to the Opcode cache, as we did for all other opcodes where the handling is otherwise the same between arm mode and thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354115 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstructionSelector.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMInstructionSelector.cpp b/lib/Target/ARM/ARMInstructionSelector.cpp index 3030e219474..0c95c21054d 100644 --- a/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/lib/Target/ARM/ARMInstructionSelector.cpp @@ -97,6 +97,8 @@ private: unsigned STORE8; unsigned LOAD8; + unsigned ADDrr; + // Used for G_ICMP unsigned CMPrr; unsigned MOVi; @@ -297,6 +299,8 @@ ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) { STORE_OPCODE(STORE8, STRBi12); STORE_OPCODE(LOAD8, LDRBi12); + STORE_OPCODE(ADDrr, ADDrr); + STORE_OPCODE(CMPrr, CMPrr); STORE_OPCODE(MOVi, MOVi); STORE_OPCODE(MOVCCi, MOVCCi); @@ -957,7 +961,7 @@ bool ARMInstructionSelector::select(MachineInstr &I, return selectShift(ARM_AM::ShiftOpc::lsl, MIB); } case G_GEP: - I.setDesc(TII.get(STI.isThumb2() ? ARM::t2ADDrr : ARM::ADDrr)); + I.setDesc(TII.get(Opcodes.ADDrr)); MIB.add(predOps(ARMCC::AL)).add(condCodeOp()); break; case G_FRAME_INDEX: -- 2.11.0