From 6aa4f1d15ca8f843d92cf8e431a03d5b1278054c Mon Sep 17 00:00:00 2001 From: Taylor Simpson Date: Thu, 27 Apr 2023 16:00:07 -0700 Subject: [PATCH] Hexagon (target/hexagon) Make special new_value for USR Precursor to moving new_value from the global state to DisasContext USR will need to stay in the global state because some helpers will set it's value Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-17-tsimpson@quicinc.com> --- target/hexagon/README | 2 +- target/hexagon/cpu.h | 1 + target/hexagon/gen_tcg_funcs.py | 2 +- target/hexagon/genptr.c | 8 ++++++-- target/hexagon/genptr.h | 1 + target/hexagon/macros.h | 2 +- target/hexagon/translate.c | 22 +++++++++++++++------- target/hexagon/translate.h | 1 + 8 files changed, 27 insertions(+), 12 deletions(-) diff --git a/target/hexagon/README b/target/hexagon/README index f86850ba73..4186f8fe3f 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -186,7 +186,7 @@ We also generate an analyze_ function for each instruction. Currently, these functions record the writes to registers by calling ctx_log_*. During gen_start_packet, we invoke the analyze_ function for each instruction in the packet, and we mark the implicit writes. After the analysis is performed, -we initialize hex_new_value for each of the predicated assignments. +we initialize the result register for each of the predicated assignments. In addition to instruction semantics, we use a generator to create the decode tree. This generation is also a two step process. The first step is to run diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 631bfdbe9c..f86c9f0131 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -90,6 +90,7 @@ typedef struct CPUArchState { uint8_t slot_cancelled; target_ulong new_value[TOTAL_PER_THREAD_REGS]; + target_ulong new_value_usr; /* * Only used when HEX_DEBUG is on, but unconditionally included diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py index 0e45d43685..a36117d57f 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -190,7 +190,7 @@ def genptr_decl_new(f, tag, regtype, regid, regno): if regid in {"s", "t"}: f.write( f" TCGv {regtype}{regid}N = " - f"hex_new_value[insn->regno[{regno}]];\n" + f"get_result_gpr(ctx, insn->regno[{regno}]);\n" ) else: print("Bad register parse: ", regtype, regid) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 5eb0d58659..bfcb962a3d 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -68,10 +68,14 @@ static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val, } } -static TCGv get_result_gpr(DisasContext *ctx, int rnum) +TCGv get_result_gpr(DisasContext *ctx, int rnum) { if (ctx->need_commit) { - return hex_new_value[rnum]; + if (rnum == HEX_REG_USR) { + return hex_new_value_usr; + } else { + return hex_new_value[rnum]; + } } else { return hex_gpr[rnum]; } diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index e11ccc2358..a4b43c2910 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -35,6 +35,7 @@ void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot); void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot); TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); +TCGv get_result_gpr(DisasContext *ctx, int rnum); TCGv get_result_pred(DisasContext *ctx, int pnum); void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val); void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val); diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 54562cccb0..828874f318 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -46,7 +46,7 @@ #define SET_USR_FIELD(FIELD, VAL) \ do { \ if (pkt_need_commit) { \ - fINSERT_BITS(env->new_value[HEX_REG_USR], \ + fINSERT_BITS(env->new_value_usr, \ reg_field_info[FIELD].width, \ reg_field_info[FIELD].offset, (VAL)); \ } else { \ diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index fe85edc1ec..e73c0066dd 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -45,6 +45,7 @@ TCGv hex_this_PC; TCGv hex_slot_cancelled; TCGv hex_branch_taken; TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; +TCGv hex_new_value_usr; TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; TCGv hex_new_pred_value[NUM_PREGS]; TCGv hex_pred_written; @@ -547,12 +548,12 @@ static void gen_start_packet(DisasContext *ctx) tcg_gen_movi_tl(hex_pred_written, 0); } - /* Preload the predicated registers into hex_new_value[i] */ + /* Preload the predicated registers into get_result_gpr(ctx, i) */ if (ctx->need_commit && !bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) { int i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); while (i < TOTAL_PER_THREAD_REGS) { - tcg_gen_mov_tl(hex_new_value[i], hex_gpr[i]); + tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]); i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS, i + 1); } @@ -667,7 +668,7 @@ static void gen_reg_writes(DisasContext *ctx) for (i = 0; i < ctx->reg_log_idx; i++) { int reg_num = ctx->reg_log[i]; - tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); + tcg_gen_mov_tl(hex_gpr[reg_num], get_result_gpr(ctx, reg_num)); /* * ctx->is_tight_loop is set when SA0 points to the beginning of the TB. @@ -1180,10 +1181,14 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, gpr[i]), hexagon_regnames[i]); - snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); - hex_new_value[i] = tcg_global_mem_new(cpu_env, - offsetof(CPUHexagonState, new_value[i]), - new_value_names[i]); + if (i == HEX_REG_USR) { + hex_new_value[i] = NULL; + } else { + snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); + hex_new_value[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, new_value[i]), + new_value_names[i]); + } if (HEX_DEBUG) { snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", @@ -1193,6 +1198,9 @@ void hexagon_translate_init(void) reg_written_names[i]); } } + hex_new_value_usr = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); + for (i = 0; i < NUM_PREGS; i++) { hex_pred[i] = tcg_global_mem_new(cpu_env, offsetof(CPUHexagonState, pred[i]), diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 26bcae0395..4c17433a6f 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -191,6 +191,7 @@ extern TCGv hex_this_PC; extern TCGv hex_slot_cancelled; extern TCGv hex_branch_taken; extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; +extern TCGv hex_new_value_usr; extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; extern TCGv hex_new_pred_value[NUM_PREGS]; extern TCGv hex_pred_written; -- 2.11.0