From 6ac1c6ccf1f8aedc6d8af4afc3b469f433bff1dc Mon Sep 17 00:00:00 2001 From: Jonas Paulsson Date: Wed, 31 Jan 2018 09:26:51 +0000 Subject: [PATCH] [PowerPC] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Nemanja Ivanovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323858 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCRegisterInfo.h | 2 ++ test/CodeGen/PowerPC/licm-tocReg.ll | 16 ++++----- test/CodeGen/PowerPC/load-two-flts.ll | 4 +-- test/CodeGen/PowerPC/ppc64-byval-align.ll | 3 +- test/CodeGen/PowerPC/select-i1-vs-i1.ll | 60 +++++++++++-------------------- 5 files changed, 33 insertions(+), 52 deletions(-) diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 0bbb71fdf9f..91a98ee4efc 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -85,6 +85,8 @@ public: BitVector getReservedRegs(const MachineFunction &MF) const override; bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override; + bool enableMultipleCopyHints() const override { return true; } + /// We require the register scavenger. bool requiresRegisterScavenging(const MachineFunction &MF) const override { return true; diff --git a/test/CodeGen/PowerPC/licm-tocReg.ll b/test/CodeGen/PowerPC/licm-tocReg.ll index efbec9091a5..e85d931c294 100644 --- a/test/CodeGen/PowerPC/licm-tocReg.ll +++ b/test/CodeGen/PowerPC/licm-tocReg.ll @@ -65,15 +65,15 @@ define signext i32 @test(i32 (i32)* nocapture %FP) local_unnamed_addr #0 { ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 6, 2, .LC0@toc@ha -; CHECK-NEXT: addis 4, 2, .LC1@toc@ha -; CHECK-NEXT: ld 5, .LC1@toc@l(4) -; CHECK-NEXT: ld 6, .LC0@toc@l(6) -; CHECK-NEXT: lwz 4, 0(5) -; CHECK-NEXT: lwz 7, 0(6) -; CHECK-NEXT: cmpw 4, 7 +; CHECK-NEXT: addis 4, 2, .LC0@toc@ha +; CHECK-NEXT: addis 5, 2, .LC1@toc@ha +; CHECK-NEXT: mr 12, 3 +; CHECK-NEXT: ld 4, .LC0@toc@l(4) +; CHECK-NEXT: ld 5, .LC1@toc@l(5) +; CHECK-NEXT: lwz 6, 0(4) ; CHECK-NEXT: lwz 7, 0(5) -; CHECK-NEXT: mr 4, 3 +; CHECK-NEXT: cmpw 6, 7 +; CHECK-NEXT: lwz 6, 0(4) ; CHECK-NEXT: bgt 0, .LBB0_2 ; CHECK-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha ; CHECK-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha diff --git a/test/CodeGen/PowerPC/load-two-flts.ll b/test/CodeGen/PowerPC/load-two-flts.ll index 157f1922c7a..584c89cc71f 100644 --- a/test/CodeGen/PowerPC/load-two-flts.ll +++ b/test/CodeGen/PowerPC/load-two-flts.ll @@ -53,8 +53,8 @@ entry: ; CHECK-NOT: ldu {{[0-9]+}}, 8(5) ; CHECK-NOT: stw ; CHECK-NOT: rldicl -; CHECK-DAG: lfsu {{[0-9]+}}, 8(5) -; CHECK-DAG: lfs {{[0-9]+}}, 4(5) +; CHECK-DAG: lfsu {{[0-9]+}}, 8(3) +; CHECK-DAG: lfs {{[0-9]+}}, 4(3) ; CHECK: blr } diff --git a/test/CodeGen/PowerPC/ppc64-byval-align.ll b/test/CodeGen/PowerPC/ppc64-byval-align.ll index 69f4759eac7..f91da59a3ac 100644 --- a/test/CodeGen/PowerPC/ppc64-byval-align.ll +++ b/test/CodeGen/PowerPC/ppc64-byval-align.ll @@ -24,8 +24,7 @@ entry: ret void } ; CHECK-LABEL: @caller1 -; CHECK: mr [[REG:[0-9]+]], 3 -; CHECK: mr 7, [[REG]] +; CHECK: mr 7, 3 ; CHECK: bl test1 define i64 @callee2(%struct.pad* byval nocapture readnone %x, i32 signext %y, %struct.test* byval align 16 nocapture readonly %z) { diff --git a/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/test/CodeGen/PowerPC/select-i1-vs-i1.ll index e8e6f99cb22..a2df1828afc 100644 --- a/test/CodeGen/PowerPC/select-i1-vs-i1.ll +++ b/test/CodeGen/PowerPC/select-i1-vs-i1.ll @@ -557,10 +557,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: fmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: fmr 1, 6 ; CHECK: blr } @@ -654,10 +652,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: fmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: fmr 1, 6 ; CHECK: blr } @@ -751,10 +747,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: fmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: fmr 1, 6 ; CHECK: blr } @@ -848,10 +842,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: fmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: fmr 1, 6 ; CHECK: blr } @@ -1327,10 +1319,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: qvfmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: qvfmr 1, 6 ; CHECK: blr } @@ -1424,10 +1414,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: qvfmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: qvfmr 1, 6 ; CHECK: blr } @@ -1521,10 +1509,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: qvfmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: qvfmr 1, 6 ; CHECK: blr } @@ -1618,10 +1604,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: qvfmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: qvfmr 1, 6 ; CHECK: blr } @@ -1715,10 +1699,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: qvfmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: qvfmr 1, 6 ; CHECK: blr } @@ -1812,10 +1794,8 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] -; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: -; CHECK: qvfmr 1, 5 +; CHECK: bclr 12, [[REG1]], 0 +; CHECK: qvfmr 1, 6 ; CHECK: blr } -- 2.11.0