From 6af2db2222a54d8e83755123f7830f9eff60507e Mon Sep 17 00:00:00 2001
From: Bradley Smith <bradley.smith@arm.com>
Date: Wed, 9 Apr 2014 14:43:40 +0000
Subject: [PATCH] [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should
 canonically be zero but should be decoded/disassembled with any value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM64/ARM64InstrFormats.td                |  4 +++-
 lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp | 12 ++++++++++++
 test/MC/Disassembler/ARM64/canonical-form.txt        |  4 ++++
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td
index 83a64dc43d7..bd16e12db78 100644
--- a/lib/Target/ARM64/ARM64InstrFormats.td
+++ b/lib/Target/ARM64/ARM64InstrFormats.td
@@ -3502,11 +3502,13 @@ class BaseOneOperandFPComparison<bit signalAllNans,
   let Inst{31-23} = 0b000111100;
   let Inst{21}    = 1;
 
-  let Inst{20-16} = 0b00000;
   let Inst{15-10} = 0b001000;
   let Inst{9-5}   = Rn;
   let Inst{4}     = signalAllNans;
   let Inst{3-0}   = 0b1000;
+
+  // Rm should be 0b00000 canonically, but we need to accept any value.
+  let PostEncoderMethod = "fixOneOperandFPComparison";
 }
 
 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
index 5d4651cf274..95020e4395e 100644
--- a/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
@@ -184,6 +184,8 @@ public:
   fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
                         const MCSubtargetInfo &STI) const;
 
+  unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
+                                     const MCSubtargetInfo &STI) const;
 };
 
 } // end anonymous namespace
@@ -588,4 +590,14 @@ ARM64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
   return EncodedValue;
 }
 
+unsigned
+ARM64MCCodeEmitter::fixOneOperandFPComparison(const MCInst &MI,
+                                              unsigned EncodedValue,
+                                              const MCSubtargetInfo &STI) const {
+  // The Rm field of FCMP and friends is unused - it should be assembled
+  // as 0, but is ignored by the processor.
+  EncodedValue &= ~(0x1f << 16);
+  return EncodedValue;
+}
+
 #include "ARM64GenMCCodeEmitter.inc"
diff --git a/test/MC/Disassembler/ARM64/canonical-form.txt b/test/MC/Disassembler/ARM64/canonical-form.txt
index ccc93e6e956..3172fd2521f 100644
--- a/test/MC/Disassembler/ARM64/canonical-form.txt
+++ b/test/MC/Disassembler/ARM64/canonical-form.txt
@@ -7,3 +7,7 @@
 0x00 0x00 0x40 0x9b
 
 # CHECK: smulh x0, x0, x0
+
+0x08 0x20 0x21 0x1e
+
+# CHECK: fcmp s0, #0.0
-- 
2.11.0