From 6b207d3cfa6b7be87ebde25c6c002f776f3d1595 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Thu, 20 Dec 2012 00:22:11 +0000 Subject: [PATCH] Target/R600: Update MIB according to r170588. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170620 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDILCFGStructurizer.cpp | 34 ++++++++++++++++++-------------- lib/Target/R600/R600InstrInfo.cpp | 12 ++++++----- lib/Target/R600/SIInstrInfo.cpp | 5 +++-- 3 files changed, 29 insertions(+), 22 deletions(-) diff --git a/lib/Target/R600/AMDILCFGStructurizer.cpp b/lib/Target/R600/AMDILCFGStructurizer.cpp index 568d281e639..9de97b62699 100644 --- a/lib/Target/R600/AMDILCFGStructurizer.cpp +++ b/lib/Target/R600/AMDILCFGStructurizer.cpp @@ -2022,7 +2022,9 @@ CFGStructurizer::normalizeInfiniteLoopExit(LoopT* LoopRep) { CFGTraits::insertAssignInstrBefore(insertPos, passRep, immReg, 1); InstrT *newInstr = CFGTraits::insertInstrBefore(insertPos, AMDGPU::BRANCH_COND_i32, passRep); - MachineInstrBuilder(newInstr).addMBB(loopHeader).addReg(immReg, false); + MachineInstrBuilder MIB(*funcRep, newInstr); + MIB.addMBB(loopHeader); + MIB.addReg(immReg, false); SHOWNEWINSTR(newInstr); @@ -2844,13 +2846,12 @@ struct CFGStructTraits { MachineInstr *oldInstr = &(*instrPos); const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); MachineBasicBlock *blk = oldInstr->getParent(); - MachineInstr *newInstr = - blk->getParent()->CreateMachineInstr(tii->get(newOpcode), - DL); + MachineFunction *MF = blk->getParent(); + MachineInstr *newInstr = MF->CreateMachineInstr(tii->get(newOpcode), DL); blk->insert(instrPos, newInstr); - MachineInstrBuilder(newInstr).addReg(oldInstr->getOperand(1).getReg(), - false); + MachineInstrBuilder MIB(*MF, newInstr); + MIB.addReg(oldInstr->getOperand(1).getReg(), false); SHOWNEWINSTR(newInstr); //erase later oldInstr->eraseFromParent(); @@ -2863,13 +2864,13 @@ struct CFGStructTraits { RegiT regNum, DebugLoc DL) { const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); + MachineFunction *MF = blk->getParent(); - MachineInstr *newInstr = - blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DL); + MachineInstr *newInstr = MF->CreateMachineInstr(tii->get(newOpcode), DL); //insert before blk->insert(insertPos, newInstr); - MachineInstrBuilder(newInstr).addReg(regNum, false); + MachineInstrBuilder(*MF, newInstr).addReg(regNum, false); SHOWNEWINSTR(newInstr); } //insertCondBranchBefore @@ -2879,11 +2880,12 @@ struct CFGStructTraits { AMDGPUCFGStructurizer *passRep, RegiT regNum) { const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); + MachineFunction *MF = blk->getParent(); MachineInstr *newInstr = - blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DebugLoc()); + MF->CreateMachineInstr(tii->get(newOpcode), DebugLoc()); blk->push_back(newInstr); - MachineInstrBuilder(newInstr).addReg(regNum, false); + MachineInstrBuilder(*MF, newInstr).addReg(regNum, false); SHOWNEWINSTR(newInstr); } //insertCondBranchEnd @@ -2928,12 +2930,14 @@ struct CFGStructTraits { RegiT src2Reg) { const AMDGPUInstrInfo *tii = static_cast(passRep->getTargetInstrInfo()); + MachineFunction *MF = blk->getParent(); MachineInstr *newInstr = - blk->getParent()->CreateMachineInstr(tii->get(tii->getIEQOpcode()), DebugLoc()); + MF->CreateMachineInstr(tii->get(tii->getIEQOpcode()), DebugLoc()); - MachineInstrBuilder(newInstr).addReg(dstReg, RegState::Define); //set target - MachineInstrBuilder(newInstr).addReg(src1Reg); //set src value - MachineInstrBuilder(newInstr).addReg(src2Reg); //set src value + MachineInstrBuilder MIB(*MF, newInstr); + MIB.addReg(dstReg, RegState::Define); //set target + MIB.addReg(src1Reg); //set src value + MIB.addReg(src2Reg); //set src value blk->insert(instrPos, newInstr); SHOWNEWINSTR(newInstr); diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp index 79bb97584e2..28637b890bc 100644 --- a/lib/Target/R600/R600InstrInfo.cpp +++ b/lib/Target/R600/R600InstrInfo.cpp @@ -72,10 +72,11 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const { MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc()); - MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); - MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X); - MachineInstrBuilder(MI).addImm(Imm); - MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT + MachineInstrBuilder MIB(*MF, MI); + MIB.addReg(DstReg, RegState::Define); + MIB.addReg(AMDGPU::ALU_LITERAL_X); + MIB.addImm(Imm); + MIB.addReg(0); // PREDICATE_BIT return MI; } @@ -449,7 +450,8 @@ R600InstrInfo::PredicateInstruction(MachineInstr *MI, if (PIdx != -1) { MachineOperand &PMO = MI->getOperand(PIdx); PMO.setReg(Pred[2].getReg()); - MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); + MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); + MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); return true; } diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 4aa4a45fb59..adcffa8bbdb 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -62,8 +62,9 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const { MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc()); - MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); - MachineInstrBuilder(MI).addImm(Imm); + MachineInstrBuilder MIB(*MF, MI); + MIB.addReg(DstReg, RegState::Define); + MIB.addImm(Imm); return MI; -- 2.11.0