From 6ba117404e4121ddd043201706f9b4b8dc718036 Mon Sep 17 00:00:00 2001 From: Jun Lei Date: Thu, 16 May 2019 15:23:20 -0400 Subject: [PATCH] drm/amd/display: fix pstate allow handling in dcn2 [why] pstate allow/block is not being handled properly on DCN2 [how] DML needs to be updated to calculate pstate support at both min and max mpc combine rather than just min clock manager needs to update current to new pstate support before sending to pplib/smu Signed-off-by: Jun Lei Reviewed-by: Dmytro Laktyushkin Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 7 +++++-- .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 12 ++++-------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index 5814cacbe1be..34402dffd2ca 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -191,10 +191,13 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); } - if (!safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) + if (!safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) { + clk_mgr_base->clks.p_state_change_support = false; pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, false); - else if (safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) + } else if (safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) { + clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); + } if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index b7edb39cd902..21d90c6f3c88 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -2592,8 +2592,9 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_unsupported; } } - for (k = 1; k <= mode_lib->vba.soc.num_states; k++) - mode_lib->vba.DRAMClockChangeSupport[k][0] = mode_lib->vba.DRAMClockChangeSupport[0][0]; + for (k = 0; k <= mode_lib->vba.soc.num_states; k++) + for (j = 0; j < 2; j++) + mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0]; //XFC Parameters: for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { @@ -5061,12 +5062,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) { mode_lib->vba.VoltageLevel = i; if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false - || mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible - || (mode_lib->vba.WhenToDoMPCCombine == dm_mpc_reduce_voltage_and_clocks - && ((locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive - && locals->DRAMClockChangeSupport[i][0] != dm_dram_clock_change_vactive) - || (locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vblank - && locals->DRAMClockChangeSupport[i][0] == dm_dram_clock_change_unsupported))))) { + || mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible)) { MaximumMPCCombine = 1; } else { MaximumMPCCombine = 0; -- 2.11.0