From 6bad4ff84cb57f548d42a41091159b750eed9ef9 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Tue, 3 May 2022 17:53:44 -0400 Subject: [PATCH] drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support [why & how] Expose vendor specific DPCD registers for rate controlling the eDP sink TCON's refresh rate during PSR active. When used in combination with PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for short. v2: Add all DPCD registers required Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h index 20a3d4e23f66..05096c644a60 100644 --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h @@ -41,6 +41,10 @@ #define DP_DEVICE_ID_38EC11 0x38EC11 #define DP_FORCE_PSRSU_CAPABILITY 0x40F +#define DP_SINK_PSR_ACTIVE_VTOTAL 0x373 +#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE 0x375 +#define DP_SOURCE_PSR_ACTIVE_VTOTAL 0x376 + enum ddc_result { DDC_RESULT_UNKNOWN = 0, DDC_RESULT_SUCESSFULL, -- 2.11.0